An error occurred fetching the project authors.
- 15 Jun, 2017 7 commits
-
-
Vivien Didelot authored
Prefix and document the remaining Global IP and IEEE Priority and Core Tag Type registers and give them a clear 16-bit register representation. Signed-off-by:
Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
-
Vivien Didelot authored
Prefix and document the Global Stats Operation and Counter registers and give them a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Control and Control 2 registers macros and give a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global VTU registers macros and give a clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global ATU Registers macros and give clear 16-bit registers representation. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Switch MAC Address Register macros and give clear 16-bit register representation. At the same time, move mv88e6xxx_g1_set_switch_mac in global1.c, where it belongs. Signed-off-by:
-
Vivien Didelot authored
Prefix and document the Global Status Register macros and give clear 16-bit register representation. Signed-off-by:
-
- 13 Jun, 2017 8 commits
-
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the remaining common Port Registers macros with MV88E6XXX_PORT. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Association Vector Register macros with MV88E6XXX_PORT_ASSOC_VECTOR. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Egress Rate Control and Port Egress Rate Control 2 registers macros with MV88E6XXX_PORT_EGRESS_RATE_CTL1 and MV88E6XXX_PORT_EGRESS_RATE_CTL2. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Control 2 Register macros with MV88E6XXX_PORT_CTL2 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6095_PORT_CTL2_CPU_PORT_MASK.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Default VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Control Register macros with MV88E6XXX_PORT_CTL0 and the ones which differ between implementations with a chosen reference model (e.g. MV88E6185_PORT_CTL0_USE_TAG.) The reason for CTL0 is to make it clear between the badly named "Port Control", "Port Control 1" and "Port Control 2" registers. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Switch ID Register macros with MV88E6XXX_PORT_SWITCH_ID. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers, this means shifting their values by 4. Signed-off-by:
-
Vivien Didelot authored
For implicit namespacing and clarity, prefix the common Port Status Register macros with MV88E6XXX_PORT_STS and the ones which differ between implementations with a chosen reference model (e.g. MV88E6352_PORT_STS_EEE.) Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by:
-
- 09 Jun, 2017 6 commits
-
-
Vivien Didelot authored
Marvell chips have a Jumbo Mode to set the maximum frame size (MTU). The mv88e6xxx_ops structure is meant to contain generic functionalities, no driver logic. Change port_jumbo_config to port_set_jumbo_size setting the mode from a given maximum size value. There is no functional changes since we still use 10240 bytes. At the same time, correctly clear all Jumbo Mode bits before writing. Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Signed-off-by:
-
Vivien Didelot authored
All Marvell chips supporting Pause frames limiting use 1-byte value for input and output. Old chips have both bytes adjacent in a 16-bit register. New ones have an indirect table using 8-bit data. The mv88e6xxx library functions (such as in port.c) must not contain driver logic, but only generic helpers. This patch changes the port_pause_config operation for port_pause_limit taking two u8 arguments for input and output limits. There is no functional changes. Reviewed-by:
-
Vivien Didelot authored
The mv88e6xxx_ops describe functionalities, regardless their locations (which can be Global1, Global2, or whatever register set.) Rename the g1_set_cpu_port and g1_set_egress_port ops to set_cpu_port and set_egress_port. No functional changes. Signed-off-by:
-
Vivien Didelot authored
Reuse the BR_STATE_* values to abstract a port STP state value. This provides shorter names and better control over the DSA switch operation call. Signed-off-by:
-
Vivien Didelot authored
As for the frame mode, add a mv88e6xxx_egress_mode enumeration instead of a 16-bit register mask. Reviewed-by:
-
Vivien Didelot authored
The mv888e6xxx driver accesses a port's netdev mostly for printing. This is bad for 2 reasons: DSA and CPU ports do not have a netdev pointer; it doesn't give us a correct picture of why a DSA driver might need to access a port's netdev. Instead simply use dev_* printing functions with chip->dev (or ds->dev depending on the scope, both guaranteed to exist), with a p%d prefix for the target port. Signed-off-by:
-
- 08 Jun, 2017 3 commits
-
-
Vivien Didelot authored
The mv88e6xxx driver currently tries to be smart and remove by itself a VLAN entry from the VTU when the driven switch sees no user ports as members of the VLAN. This is bad in a multi-chip switch fabric, since a chip in between others may have no bridge port members, but still needs to be aware of the VID in order to correctly pass frames in the data path. Now that the DSA core explicitly manages DSA and CPU ports, do not skip them when checking remaining VLAN members. Signed-off-by:
-
Vivien Didelot authored
Now that the DSA core adds the CPU and DSA ports itself to the new VLAN entry, there is no need to include them as members of this VLAN when initializing a new VTU entry. As of now, initialize a new VTU entry with all ports excluded. Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
-
Vivien Didelot authored
Define the target port membership of the VLAN entry in mv88e6xxx_port_vlan_add where ds is scoped. Allow the DSA core to call later the port_vlan_add operation for CPU or DSA ports, by using the Unmodified membership for these ports, as in the current behavior. Reviewed-by:
-
- 07 Jun, 2017 1 commit
-
-
Andrew Lunn authored
The mv88e6161 and mv88e6123 are capable of using EDSA tags when passing frames from the host to the switch and back. Signed-off-by:
-
- 05 Jun, 2017 3 commits
-
-
Andrew Lunn authored
The mv88e6161 was using the wrong method to perform statistics snapshot. Signed-off-by:
-
Andrew Lunn authored
Access to the internal PHYs of the 6161 and 6123 go through global 2 SMI registers. Fix the ops structure. Signed-off-by:
-
Vivien Didelot authored
The mv88e6xxx.h is meant to contains the chip structures and data. Rename it to chip.h, as for other source/header pairs of the driver. At the same time, ensure that relative header inclusions are separated by a newline and sorted alphabetically. Signed-off-by:
-
- 31 May, 2017 3 commits
-
-
Vivien Didelot authored
The current dsa_register_switch function takes a useless struct device pointer argument, which always equals ds->dev. Drivers either call it with ds->dev, or with the same device pointer passed to dsa_switch_alloc, which ends up being assigned to ds->dev. This patch removes the second argument of the dsa_register_switch and _dsa_register_switch functions. Signed-off-by:
-
Vivien Didelot authored
Make it clear that mv88e6xxx_phy_ppu_{read,write} are an implementation of the .phy_{read,write} operations, by renaming them with the mv88e6185 prefix, since 88E6185 it is the reference switch model supported in an upstream board (ZII Dev Rev B), which makes use of them. Distinguish the signatures of implementation specific and generic PHY functions in the phy.h header. Signed-off-by: -
Vivien Didelot authored
Similarly to the VTU, PVT and ATU setup, provide a mv88e6xxx_phy_setup helper which wraps mv88e6xxx_ppu_enable, so that no more PPU-related functions are exposed outside of phy.c. Thus make mv88e6xxx_ppu_enable static. Signed-off-by:
-
- 27 May, 2017 1 commit
-
-
Vivien Didelot authored
mv88e6xxx_serdes_power returns an error, so no need to print an error message inside of it. Rather print it in its caller when the error is ignored, which is in the mv88e6xxx_port_disable void function. Catch and return its error in the counterpart mv88e6xxx_port_enable. Fixes: 04aca993 ("dsa: mv88e6xxx: Enable/Disable SERDES on port enable/disable") Signed-off-by:
-
- 26 May, 2017 4 commits
-
-
Andrew Lunn authored
Implement the port enable/disable callbacks, which enable/disable the SERDES interfaces, if applicable. This should save a bit of power/heat. We also need to enable SERDES on CPU and DSA ports, so keep the existing call to the op, but make it conditional. Signed-off-by:
-
Andrew Lunn authored
The mv88e6390X family has 8 SERDES lanes. These can be used for 2 10Gbps ports, ports 9 or 10. If these ports are used at slower speeds, the SERDES lanes become available for other ports for 1000Base-X. Signed-off-by:
-
Andrew Lunn authored
The mv88e6390 family has a different SERDES implementation. Refactor the mv88e6352 code into an ops function, so we can later add the mv88e6390 code. Signed-off-by:
-
Andrew Lunn authored
The upcoming SERDES support will need to make use of PHY functions. Move them out into a file of there own. No code changes. Signed-off-by:
-
- 18 May, 2017 2 commits
-
-
Vivien Didelot authored
Now that the DSA public header includes switchdev.h, use the provided switchdev_obj_dump_cb_t typedef for the object dump callback. Signed-off-by:
-
Vivien Didelot authored
DSA drivers and core use switchdev. Include switchdev.h only once, in the dsa.h public header, so that inclusion in DSA drivers or forward declarations of switchdev structures in not necessary anymore. Signed-off-by:
-
- 12 May, 2017 1 commit
-
-
Gustavo A. R. Silva authored
Add default case to switch in order to avoid any chance of using an uninitialized variable _low_, in case s->type does not match any of the listed case values. Addresses-Coverity-ID: 1398130 Suggested-by:
Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by:
-
- 01 May, 2017 1 commit
-
-
Vivien Didelot authored
The 6390 family of chips use only 2 of the 3 VTU Data registers to pack the MemberTag and PortState VLAN data. This means that they must be written or read before or after each VTU/STU operations. Implement this variant to add support for VTU with such chips. These chips have a 13th bit for the VID thus set their max_vid to 8191. Signed-off-by:
-
