- 15 Aug, 2019 35 commits
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Nikola Cornij authored
[why] At the time DIG FE is connected to its BE, the clocks in OTG are enabled and PHY will also be set up. When DSC has to be used to fit the stream into the available bandwidth, without DSC being set DIG could get exposed to the higer bandwidth it (or link) could handle. This causes the HW to "reject" video enable setup (the register shows that video enable was attempted, but the status bit shows it as disabled). [how] - Separate DSC setup into DSC register config and DSC PPS SDP setup - Move most of the DSC setup (register config) to before dcn10_link_encoder_connect_dig_be_to_fe() is called - Set up DSC PPS SDP after DIG FE is connected to its BE. This is because setting DSC PPS SDP before that has no effect. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nikola Cornij authored
[why] Minimum slice height is recommended by VESA DSC Spreadsheet user guide Signed-off-by:
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Vitaly Prosyak authored
[Why & How] Support hlg OETF and EOTF based on BT.2100-2 Follow up is required. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Jun Lei authored
[why] Previous "less risky" implemenation of 3 tiered fallback is no longer necessary since DMLv2 has gone through proper validation. v2 can now be used as the default and 1 level of fallback can be removed [how] remove previous workaround implemenation Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Martin Leung authored
[Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes [How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock. This is part 2 of 2 for seamless boot NV10 Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
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Martin Leung authored
[Why] underflow seen on certain monitor setups caused by making dcnxx_init_hw generic [How] by moving dcn20_init_hw into dcn10, we added a dcn-specific clk_mgr init (dc->clk_mgr->funcs->init_clocks()). Thus, put old clk_mgr memset in an else statement so both memsets don't get set Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Leung authored
[Why] For seamless boot the init_hw sequence must be split into actual hardware vs pipes, in order to defer pipe initialization to set mode and skip of pipe-destructive sequences [How] made dcn10_init_hw and dcn10_init_pipes generic for future dcns to inherit deleted dcn20 specific versions. This is part 1 of a 2 partimplementation of seamless boot Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Jun Lei authored
[why] When planes are enabled, they must be enabled using VSYNC update (not immediate). However, before the VUPDATE occurs, DM may call with an "immediate" flip which is address only. This operation would normally be okay, but if the locking for immediate flip happens to occur before the VUPDATE associated with the initial plane enablement, it will cause HW to hang. [how] HWSS should enforce plane enable in HW to be synchronous with the call that enables the plane. Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Su Sung Chung authored
[why] if dynamic allocation fails during gpio_open, it will cause crash due to page fault. [how] handle allocation when gpio object gets created and prevent from calling gpio_open if allocation failed Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Jaehyun Chung authored
[Why] Auto Overclock Memory fails for some systems that don't support p-state. [How] Implement the workaround, and it's corresponding enable flag. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Jun Lei authored
[why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by:
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Dmytro Laktyushkin authored
Currently every time DC wants to access firmware info we make a call into VBIOS. This makes no sense as there is nothing that can change runtime inside fw info and can cause issues when calling unstable bios during bringup. This change eliminate this behavior by only calling bios once for fw info and keeping it stored as part of dc_bios. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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David Galiffi authored
[WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by:
David Galiffi <david.galiffi@amd.com> Reviewed-by:
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Julian Parkin authored
Add DCN20 common register list that contains registers shared between DCN20 generations. Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Vitaly Prosyak authored
[Why & How] Support degamma ROM and RAM based on hardware capabilities. Some refactoring into color module Signed-off-by:
Gary Kattan <Gary.Kattan@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Bayan Zabihiyan authored
[Why] The math on deciding on how many "frames to insert" sometimes sent us over the max refresh rate. Also integer overflow can occur if we have high refresh rates. [How] Instead of clipping the frame duration such that it doesn’t go below the min, just remove a frame from the number of frames to insert. + Use unsigned long long for intermediate calculations to prevent integer overflow. Signed-off-by:
Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] When endpoint is at the boundary of a region, such as at 2^0=1 we find that the last segment has a sharp slope and some points are clipped at the top. [How] If end point is 1, which is exactly at the 2^0 region boundary, we need to program an additional region beyond this point. Signed-off-by:
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Wenjing Liu authored
[why] hdmi data scramble and tmds rate is not reset during pipe reset. [how] reset hdmi tmds rate and data scramble on pipe reset Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
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Wenjing Liu authored
[why] drr is still enabled after driver is unloaded causing black screen [how] disable drr during pipe reset. Signed-off-by:
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Yongqiang Sun authored
Add to clk_mgr_internal struct, for future use. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Yongqiang Sun authored
For use by future ASICs Signed-off-by:
Sung Lee <sung.lee@amd.com> Signed-off-by:
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Christian König authored
The spsc_queue_peek function is accessing queue->head which belongs to the consumer thread and shouldn't be accessed by the producer This is fixing a rare race condition when destroying entities. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Monk.liu@amd.com Signed-off-by:
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Stephen Rothwell authored
Fixes: 6a7a0bdb ("drm/amdgpu: add psp_v12_0 for renoir (v2)") Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a pr_err error message. Fix it. Also add a space after a comma to clean up a checkpatch warning. Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Tao Zhou authored
get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Signed-off-by:
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Kevin Wang authored
simplify driver code. Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Kevin Wang authored
fix typo error: change function name from "amdgput_ctx_total_num_entities" to "amdgpu_ctx_total_num_entities". Signed-off-by:
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Kevin Wang authored
the direct send message to smc to set hard clokc will failed when smc clock dpm feature is disabled. so use function of smu_set_hard_freq_range to replace it. the function will check feature enablement. eg: when uclk (mclk) dpm feature is disabled on navi10 [ 300.675901] amdgpu: [powerplay] failed send message: SetHardMinByFreq(28) param: 0x00020064 response 0xfffffffb Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Chengming Gui authored
add arcturus_is_dpm_running function Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
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Chengming Gui authored
remove redundancy debug log about smu unsupported features Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
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Christoph Hellwig authored
amdgpu uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
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Christoph Hellwig authored
radeon uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
Atish Patra <Atish.Patra@wdc.com> Signed-off-by:
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- 12 Aug, 2019 5 commits
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Alex Deucher authored
The current code won't likely work on production hw when it ships so leave it as experimental until it's ready. Acked-by:
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Huang Rui authored
Renoir need not load mec2 jump table with psp. Acked-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Huang Rui authored
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by:
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Aaron Liu authored
By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP. Acked-by:
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Aaron Liu authored
enable gfx_v9_0_init_lbpw for renoir Acked-by:
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