Add support for the pin controller block on SM6115's Low Power Island.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-2-d4883831a858@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add bindings for pin controller in SM6115 Low Power Audio SubSystem
LPASS).
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230722-topic-6115_lpasstlmm-v2-1-d4883831a858@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add support to handle 'output-enable' and 'bias-high-impedance'
configurations.

Using these pinctrl properties observed hang issues with older PMUFW(Xilinx
ZynqMP Platform Management Firmware), hence reverted the patch.
Commit 9989bc33 ("Revert "pinctrl: pinctrl-zynqmp: Add support
for output-enable and bias-high-impedance"").

Support for configuring these properties added in PMUFW Configuration Set
version 2.0. When there is a request for these configurations from pinctrl
driver for ZynqMP platform, xilinx firmware driver checks for this version
before configuring these properties to avoid the hang issue and proceeds
further only when firmware version is >=2 otherwise it returns error.
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-5-sai.krishna.potthuri@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add 'output-enable' configuration parameter to the properties list.

Using these pinctrl properties observed hang issues with older Xilinx
ZynqMP Platform Management Firmware, hence reverted the patch previously.
Commit ff835606 ("Revert "dt-bindings: pinctrl-zynqmp: Add
output-enable configuration"").

Support for configuring these properties added in Xilinx ZynqMP Platform
Management firmware(PMUFW) Configuration Set version 2.0. Linux firmware
driver checks if the configuration is supported by the PMUFW when it gets
request for TRISTATE configuration from pinctrl driver. If it supports,
then calls will be made otherwise it returns error.
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-4-sai.krishna.potthuri@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Support for configuring TRISTATE parameter is added in ZYNQMP PMUFW(Xilinx
ZynqMP Platform Management Firmware) Configuration Param Set version 2.0.
If the requested configuration is TRISTATE and platform is ZYNQMP then
check the version before requesting Xilinx firmware to set the
configuration.
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-3-sai.krishna.potthuri@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add function to get family code and sub family code from the idcode. This
family code and sub family code helps to identify the platform.
Family code of any platform is on bits 21 to 27 and Sub family code is on
bits 19 and 20.
Signed-off-by: Dhaval Shah <dhaval.r.shah@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20230731095026.3766675-2-sai.krishna.potthuri@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Merge tag 'renesas-pinctrl-for-v6.6-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.6

  - Use the new devm_clk_get_enabled() helper.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl_generic_add_function() doesn't check result of radix_tree_insert()
despite they both may return a negative error code.  Linus Walleij said he
has copied the radix tree code from kernel/irq/ where the functions calling
radix_tree_insert() are *void* themselves; I think it makes more sense to
propagate the errors from radix_tree_insert() upstream if we can do that...

Found by Linux Verification Center (linuxtesting.org) with the Svace static
analysis tool.
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Link: https://lore.kernel.org/r/20230719202253.13469-4-s.shtylyov@omp.ruSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl_register_one_pin() doesn't check the result of radix_tree_insert()
despite they both may return a negative error code.  Linus Walleij said he
has copied the radix tree code from kernel/irq/ where the functions calling
radix_tree_insert() are *void* themselves; I think it makes more sense to
propagate the errors from radix_tree_insert() upstream if we can do that...

Found by Linux Verification Center (linuxtesting.org) with the Svace static
analysis tool.
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Link: https://lore.kernel.org/r/20230719202253.13469-3-s.shtylyov@omp.ruSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

pinctrl_generic_add_group() doesn't check the result of radix_tree_insert()
despite they both may return a negative error code.  Linus Walleij said he
has copied the radix tree code from kernel/irq/ where the functions calling
radix_tree_insert() are *void* themselves; I think it makes more sense to
propagate the errors from radix_tree_insert() upstream if we can do that...

Found by Linux Verification Center (linuxtesting.org) with the Svace static
analysis tool.
Signed-off-by: Sergey Shtylyov <s.shtylyov@omp.ru>
Link: https://lore.kernel.org/r/20230719202253.13469-2-s.shtylyov@omp.ruSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The devm_clk_get_enabled() helper:
   - calls devm_clk_get()
   - calls clk_prepare_enable() and registers what is needed in order to
     call clk_disable_unprepare() when needed, as a managed resource.

This simplifies the code and avoids the need of a dedicated function used
with devm_add_action_or_reset().

While at it, use dev_err_probe() which filters -EPROBE_DEFER.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a4a586337d692f0ca396b80d275ba634eb419593.1690058500.git.christophe.jaillet@wanadoo.fr
[geert: Make clk local to rzg2l_pinctrl_probe()]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Simplify clock handling by using the devm_clk_get_enabled() helper,
instead of open-coding the same operations.  Move the clock pointer from
the driver-private data to a local variable, as it is not needed outside
the .probe() callback.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cca0b1795fd0335401bdf2be393ab84445e04095.1688396836.git.geert+renesas@glider.be

On some systems amd_pinconf_set() is called with parameters
0x8 (PIN_CONFIG_DRIVE_PUSH_PULL) or 0x14 (PIN_CONFIG_PERSIST_STATE)
which are not supported by pinctrl-amd.

Don't show an err message when called with an invalid parameter,
downgrade this to debug instead.

Cc: stable@vger.kernel.org # 6.1
Fixes: 635a750d ("pinctrl: amd: Use amd_pinconf_set() for all config options")
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230717201652.17168-1-mario.limonciello@amd.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add a new pinctrl driver for Amlogic C3 SoCs which share
the same register layout as the previous Amlogic S4.
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Link: https://lore.kernel.org/r/20230714122441.3098337-3-huqiang.qin@amlogic.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add a new compatible name for Amlogic C3 pin controller, and add
a new dt-binding header file which document the detail pin names.
Signed-off-by: Huqiang Qin <huqiang.qin@amlogic.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714122441.3098337-2-huqiang.qin@amlogic.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This property was introduced as a bad hack. Now that it's useless, get
rid of it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-2-dc18b5bd14f7@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Some platforms provide a single clock source to all LPASS peripherals,
others provide two, and there are probably others that provide it through
magic invisible-to-Linux wires.

Rely on bindings to mandate the adequate number of clocks necessary.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230714-topic-lpass_lpi_cleanup-v1-1-dc18b5bd14f7@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The current function for a given pin is not displayed via the debugfs.
Add support to display the current function that is set for each pin.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20230714113547.15384-1-pshete@nvidia.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

The sunxi pinctrl has a fixed size array it uses to store regulators used
in the driver. There is currently nothing that ensures that the number of
elements in the array is large enough to map the regulators defined by the
individual SoCs. While this is currently the case having an explicit check
in there will make life easier for anyone debugging memory issues that
manifest in the driver so let's add one.
Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20230712-pinctrl-sunxi-boudns-v1-1-85f37de79b9f@kernel.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This patch adds support for an optional "reset" GPIO pin in the cy8c95x0
pinctrl driver. On probe, the reset pin is pulled low to bring chip out
of reset. The reset pin has an internal pull-down and can be left
floating if not required.

The datasheet doesn't mention any timing related to the reset pin.

Based on empirical tests, it was found that the chip requires a
delay of 250 milliseconds before accepting I2C transfers after driving
the reset pin low. Therefore, a delay of 250ms is added before
proceeding with I2C transfers.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Link: https://lore.kernel.org/r/20230714081902.2621771-2-Naresh.Solanki@9elements.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

This patch adds support for an optional reset pin.

The reset pin is used to bring the chip into a known state and has an
internal pull-down, allowing it to be left floating if not needed.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230714081902.2621771-1-Naresh.Solanki@9elements.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Allow gpio hog subnodes to the gpio subnode.

Fixes: 94df03a4 ("dt-bindings: pinctrl: Convert Amlogic Meson pinctrl binding")
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230707-topic-amlogic-upstream-pinctrl-fix-bindings-v2-2-2160060446d7@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Allow gpio-line-names property for the gpio subnodes.

Fixes: 94df03a4 ("dt-bindings: pinctrl: Convert Amlogic Meson pinctrl binding")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230707-topic-amlogic-upstream-pinctrl-fix-bindings-v2-1-2160060446d7@linaro.orgSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230704124742.9596-4-frank.li@vivo.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230704124742.9596-3-frank.li@vivo.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230704124742.9596-2-frank.li@vivo.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Convert platform_get_resource(), devm_ioremap_resource() to a single
call to devm_platform_get_and_ioremap_resource(), as this is exactly
what this function does.
Signed-off-by: Yangtao Li <frank.li@vivo.com>
Link: https://lore.kernel.org/r/20230704124742.9596-1-frank.li@vivo.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

pmx75 pmic support gpio controller so add compatible in the driver.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1688707209-30151-5-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

pm7550ba pmic support gpio controller so add compatible in the driver.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1688707209-30151-4-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add support for the pmx75 GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1688707209-30151-3-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Add support for the pm7550ba GPIO support to the Qualcomm PMIC GPIO
binding.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/1688707209-30151-2-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: Linus Walleij <linus.walleij@linaro.org>

Currently, sd1 and sd0 have unique subnode names 'sd1_mux' and 'sd0_mux'.
If we change these to non-unique subnode names such as 'mux' this can
lead to the below conflict as the RZ/G2L pin control driver considers
only the names of the subnodes.

   pinctrl-rzg2l 11030000.pinctrl: pin P47_0 already requested by 11c00000.mmc; cannot claim for 11c10000.mmc
   pinctrl-rzg2l 11030000.pinctrl: pin-376 (11c10000.mmc) status -22
   pinctrl-rzg2l 11030000.pinctrl: could not request pin 376 (P47_0) from group mux  on device pinctrl-rzg2l
   renesas_sdhi_internal_dmac 11c10000.mmc: Error applying setting, reverse things back

Fix this by constructing unique names from the node names of both the
pin control configuration node and its child node, where appropriate.

Based on the work done by Geert for the RZ/V2M pinctrl driver.

Fixes: c4c4637e ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230704111858.215278-1-biju.das.jz@bp.renesas.comSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

The eMMC and SDHI pin control configuration nodes in DT have subnodes
with the same names ("data" and "ctrl").  As the RZ/V2M pin control
driver considers only the names of the subnodes, this leads to
conflicts:

    pinctrl-rzv2m b6250000.pinctrl: pin P8_2 already requested by 85000000.mmc; cannot claim for 85020000.mmc
    pinctrl-rzv2m b6250000.pinctrl: pin-130 (85020000.mmc) status -22
    renesas_sdhi_internal_dmac 85020000.mmc: Error applying setting, reverse things back

Fix this by constructing unique names from the node names of both the
pin control configuration node and its child node, where appropriate.

Reported by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>

Fixes: 92a9b825 ("pinctrl: renesas: Add RZ/V2M pin and gpio controller driver")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Link: https://lore.kernel.org/r/607bd6ab4905b0b1b119a06ef953fa1184505777.1688396717.git.geert+renesas@glider.be

We just sorted the entries and fields last release, so just out of a
perverse sense of curiosity, I decided to see if we can keep things
ordered for even just one release.

The answer is "No. No we cannot".

I suggest that all kernel developers will need weekly training sessions,
involving a lot of Big Bird and Sesame Street.  And at the yearly
maintainer summit, we will all sing the alphabet song together.

I doubt I will keep doing this.  At some point "perverse sense of
curiosity" turns into just a cold dark place filled with sadness and
despair.

Repeats: 80e62bc8 ("MAINTAINERS: re-sort all entries and fields")
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Pull dma-mapping fixes from Christoph Hellwig:

 - swiotlb area sizing fixes (Petr Tesarik)

* tag 'dma-mapping-6.5-2023-07-09' of git://git.infradead.org/users/hch/dma-mapping:
  swiotlb: reduce the number of areas to match actual memory pool size
  swiotlb: always set the number of areas before allocating the pool

Pull irq update from Borislav Petkov:

 - Optimize IRQ domain's name assignment

* tag 'irq_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqdomain: Use return value of strreplace()

Pull x86 fpu fix from Borislav Petkov:

 - Do FPU AP initialization on Xen PV too which got missed by the recent
   boot reordering work

* tag 'x86_urgent_for_v6.5_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/xen: Fix secondary processors' FPU initialization

Pull x86 fix from Thomas Gleixner:
 "A single fix for the mechanism to park CPUs with an INIT IPI.

  On shutdown or kexec, the kernel tries to park the non-boot CPUs with
  an INIT IPI. But the same code path is also used by the crash utility.
  If the CPU which panics is not the boot CPU then it sends an INIT IPI
  to the boot CPU which resets the machine.

  Prevent this by validating that the CPU which runs the stop mechanism
  is the boot CPU. If not, leave the other CPUs in HLT"

* tag 'x86-core-2023-07-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/smp: Don't send INIT to boot CPU