- 04 May, 2022 40 commits
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Tianci.Yin authored
Add support for GPU memory controller v11. v1: Add support for gmc v11.0 Add gmc 11 block (Tianci) v2: drop unused amdgpu_bo_late_init (Hawking) v3: squash in various fix Signed-off-by:Tianci.Yin <tianci.yin@amd.com> Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Jack Xiao authored
MES firmware needs the setting of VM_CONTEXT_CNTL to perform vmid switch. Save the initial setting when hub initializing. Signed-off-by:
Jack Xiao <Jack.Xiao@amd.com> Reviewed-by:
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Tianci.Yin authored
Add support for mmhub v3.0 Signed-off-by:
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Hawking Zhang authored
Add mmhub v3_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Tianci.Yin authored
Add support for gfxhub v3.0 Signed-off-by:
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Tianci.Yin authored
Add support for athub v3.0 Signed-off-by:
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Hawking Zhang authored
Add athub v3_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Likun Gao authored
Enable PSP on PSP IP version 13.0.0 Signed-off-by:
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Likun Gao authored
Add parmeter to shows whether SCPM feature is enabled or not, and whether is valid. Signed-off-by:
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Likun Gao authored
Use the new helper for deriving the fw name from the IP version. Signed-off-by:
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Likun Gao authored
Support psp v13_0_0 microcode init. Signed-off-by:
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Likun Gao authored
Support for spl firmware load on psp v13. Signed-off-by:
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Likun Gao authored
Extend PSP GFX FW type to support IMU, LSDMA, SDMA v6, RS64 MES related fw load. Signed-off-by:
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Hawking Zhang authored
print out psp firmware v2_0 hdr information for debugging purpose Signed-off-by:
Le Ma <le.ma@amd.com> Signed-off-by:
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Alice Wong authored
psp_load_fw failure would cause memory leak for psp tmr and psp ring because psp_hw_init is not called as psp block is not fully initialized. Clean up psp tmr and psp ring when psp_load_fw fail by calling psp_free_shared_bufs and psp_ring_destroy. Reviewed-by:
Alice Wong <shiwei.wong@amd.com> Signed-off-by:
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Alex Deucher authored
So we can properly clean up if any of the TAs or TMR fails to properly initialize or terminate. This avoids any memory leaks in the error case. Reviewed-by:
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Alex Deucher authored
Make sure we free the memory even if the unload fails. Reviewed-by:
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Alex Deucher authored
Just call the load/unload/init_shared_buf functions directly. Makes the code easier to follow. Reviewed-by:
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Elena Sakhnovitch authored
On Sienna Cichild, not all platforms use PMFW based fan control (ex: fanless systems). On such ASICs fan control by PMFW will be disabled in PPTable. Disable hwmon knobs for fan control also as it is not possible to report or control fan speed on such platforms through driver. v3: FeaturesToRun casted as uint64_t Signed-off-by:
Elena Sakhnovitch <elena.sakhnovitch@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Hawking Zhang authored
initialize smuio callback for soc21 Signed-off-by:
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Alex Deucher authored
Memory allocations should be done in sw_init. hw_init should just be hardware programming needed to initialize the IP block. This is how most other IP blocks work. Move the GPU memory allocations from psp hw_init to psp sw_init and move the memory free to sw_fini. This also fixes a potential GPU memory leak if psp hw_init fails. Reviewed-by:
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Hawking Zhang authored
add smuio v13_0_6 callbacks to support read rom image Signed-off-by:
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Hawking Zhang authored
Add smuio v13_0_6 register offset and shift masks header files (Hawking) Signed-off-by:
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Elena Sakhnovitch authored
Clean up trailing space in file sienna_cichlid_ppt.c. Signed-off-by:
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Likun Gao authored
Enable HDP v6 on asics where it is present. Signed-off-by:
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Likun Gao authored
Unify hdp related function into hdp structure for hdp version 6. V2: Remove hdp invalidate function as hdp v6 doesn't have read cache. Signed-off-by:
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Philip Yang authored
To cleanup the BOs of bo_list which have got user pages. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Hawking Zhang authored
Add hdp v6_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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pengfuyuan authored
Fix spelling typo in comments. Signed-off-by:
pengfuyuan <pengfuyuan@kylinos.cn> Signed-off-by:
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Minghao Chi authored
Simplify the return expression. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Minghao Chi <chi.minghao@zte.com.cn> Signed-off-by:
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Minghao Chi authored
Simplify the return expression. Reported-by:
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Likun Gao authored
Enable IH v6 on asics where it is present. Signed-off-by:
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Stanley.Yang authored
This adds ih v6_0 ip block support. IH is the interrupt handler. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Likun Gao authored
Only V13.0.2 on SMU v13 will get 0 based max level from fw and increment by one, other ASIC will not need for this. V2: replace the asic_type check with ip versioning check. Signed-off-by:
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Stanley Yang authored
Define soc21 ih clientid Signed-off-by:
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Hawking Zhang authored
Add osssys v6_0_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Likun Gao authored
Enable NBIO 4.3 on asics where it is present. Signed-off-by:
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Stanley.Yang authored
This adds nbio v4_3_0 ip block support Changed from v1: use WREG32_SOC15/RREG32_SOC15 instead of WREG32_PCIE/RREG32_PCIE remove the programming of PCIE_CONFIG_CNTL Signed-off-by:
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Hawking Zhang authored
Add nbio v4_3_0 register offset and shift masks header files (Hawking) Signed-off-by:
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Likun Gao authored
Enable soc21 common support on asics where it is present. Signed-off-by:
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