- 06 Dec, 2017 1 commit
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Pixel Ding authored
Retry at drm_dev_register instead of amdgpu_device_init. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Pixel Ding <Pixel.Ding@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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- 04 Dec, 2017 39 commits
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Harry Wentland authored
We no longer set the framebuffer address here so this is now dead code. Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Monk Liu authored
if app close CTX right after IB submit, gpu recover will fail to find out the entity behind this guilty job thus lead to no job skipping for this guilty job. to fix this corner case just move the increasement of job->karma out of the entity iteration. v2: only do karma increasment if bad->s_priority != KERNEL because we always consider KERNEL job be correct and always want to recover an unfinished kernel job (sometimes kernel job is interrupted by VF FLR or other GPU hang event) Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
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Monk Liu authored
Signed-off-by:
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pding authored
It introduces 900ms latency in exclusive mode which causes failure of driver loading. Host can resize the BAR before guest staring, so the resizing is not necessary here. Signed-off-by:
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pding authored
Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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pding authored
Also finalize kfd inside amdgpu_device_fini. kfd device_init needs SRIOV exclusive accessing. Try to gather exclusive accessing to reduce time consuming. Signed-off-by:
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Christian König authored
Just allocate the GART space and fill it. This prevents forcing the BO to be idle. v2: don't unbind/bind at all, just fill the allocated GART space Signed-off-by:
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Christian König authored
We actually don't bind here, but rather allocate GART space if necessary. Signed-off-by:
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Hawking Zhang authored
Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Christian König authored
Try to resize BAR0 to let CPU access all of VRAM. v2: rebased, style cleanups, disable mem decode before resize, handle gmc_v9 as well, round size up to power of two. v3: handle gmc_v6 as well, release and reassign all BARs in the driver. v4: rename new function to amdgpu_device_resize_fb_bar, reenable mem decoding only if all resources are assigned. v5: reorder resource release, return -ENODEV instead of BUG_ON(). v6: squash in rebase fix Signed-off-by: -
Horace Chen authored
The previous solution will create a zero buffer on the system domain and then move the zeroes to the VRAM. This will break the original data on the VRAM. Refine the code to create bo on VRAM domain directly and then remove and re-create mem node to the exact position before bo_pin. This can avoid breaking the data and will not cause eviction. Signed-off-by:
Horace Chen <horace.chen@amd.com> Reviewed-by:
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pding authored
This is caused of that hypervisor fails to handle request, one known issue is MMIO unblocking timeout. In theory we can retry init here. Signed-off-by:
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pding authored
Reported-by:
Sun Gary <Gary.Sun@amd.com> Signed-off-by:
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Michel Dänzer authored
It's dead code. Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Michel Dänzer authored
Not used anymore. Signed-off-by:
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Michel Dänzer authored
Corresponding to the previous non-DC change. Signed-off-by:
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Michel Dänzer authored
Hardcoding the maximum numbers could result in spurious error messages from the IRQ state callbacks, e.g. on Polaris 11/12: [drm:dce_v11_0_set_pageflip_irq_state [amdgpu]] *ERROR* invalid pageflip crtc 5 [drm:amdgpu_irq_disable_all [amdgpu]] *ERROR* error disabling interrupt (-22) Signed-off-by:
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Harry Wentland authored
We'll need it in amdgpu_dm_mst_types.c as well. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Tony Cheng authored
Signed-off-by:
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Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Yue Hin Lau authored
fix memory leak Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
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Anthony Koo authored
Need to move HDR Metadata from Surface to Stream since there is only one infoframe possible per stream. Also cleaning up some duplicate definitions. Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Yue Hin Lau authored
instantiating new structure hubbub in resource.c Signed-off-by:
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Tony Cheng authored
Signed-off-by:
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Yongqiang Sun authored
Add disable ttu interface to dcn10, when remove mpc, disable ttu as well. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Yongqiang Sun authored
Since front end is programmed before back end programming, no need to reset front end in back end programming. Signed-off-by:
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Yongqiang Sun authored
front end is initialized during init_hw, but not power gated. There are some left over valuse and will cause some diags test failed. Power gated all front end pipes will make sure every test has same starting point. Signed-off-by:
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Andrew Jiang authored
We should be sticking with the default clock values if the values obtained from PPLib are bogus. Signed-off-by:
Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by:
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Yue Hin Lau authored
moving hubbub functions to new file Signed-off-by:
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Leo (Sunpeng) Li authored
Abandon new_crtcs array and use for_each_new iterator to acquire new crtcs. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
For better readability. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Christian König authored
The GTT manager handles the GART address space anyway, so it is completely pointless to keep the same information around twice. v2: rebased Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
Rename amdgpu_gtt_mgr_is_allocated() to amdgpu_gtt_mgr_has_gart_addr() and use that instead. v2: rename the function as well. Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Monk Liu authored
for SR-IOV when doing gpu reset this routine shouldn't do resource allocating otherwise memory leak Signed-off-by:
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Monk Liu authored
1,no sriov check since gpu recover is unified 2,need CPU_ACCESS_REQUIRED flag for VRAM if SRIOV because otherwise after following PIN the first allocated VRAM bo is wasted due to some TTM mgr reason. Signed-off-by:
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Monk Liu authored
since now gpu reset is unified with gpu_recover for both bare-metal and SR-IOV: 1)rename in_sriov_reset to in_gpu_reset 2)move lock_reset from adev->virt to adev Signed-off-by:
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