- 13 May, 2016 40 commits
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Huacai Chen authored
New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by:
Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Huacai Chen authored
Loongson-3A R2 has pwbase/pwfield/pwsize/pwctl registers in CP0 (this is very similar to HTW) and lwdir/lwpte/lddir/ldpte instructions which can be used for fast TLB refill. [ralf@linux-mips.org: Resolve conflict.] Signed-off-by:
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Huacai Chen authored
Loongson-2 has a 4 entry itlb which is a subset of jtlb, Loongson-3 has a 4 entry itlb and a 4 entry dtlb which are subsets of jtlb. We should write diag register to invalidate itlb/dtlb when flushing jtlb because itlb/dtlb are not totally transparent to software. For Loongson-3A R2 (and newer), we should invalidate ITLB, DTLB, VTLB and FTLB before we enable/disable FTLB. Signed-off-by:
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Huacai Chen authored
Loongson-3 maintains cache coherency by hardware, this means: 1) It's icache is coherent with dcache. 2) It's dcaches don't alias (maybe depend on PAGE_SIZE). 3) It maintains cache coherency across cores (and for DMA). So we can skip most cache flush operations by setting relevant handlers to `cache_noop' in `r4k_cache_init'. Signed-off-by:
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Huacai Chen authored
Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R2 revision of Loongson-3A: - Primary cache includes I-Cache, D-Cache and V-Cache (Victim Cache). - I-Cache, D-Cache and V-Cache are 16-way set-associative, linesize is 64 bytes. - 64 entries of VTLB (classic TLB), 1024 entries of FTLB (8-way set-associative). - Supports DSP/DSPv2 instructions, UserLocal register and Read-Inhibit/ Execute-Inhibit. [ralf@linux-mips.org: Resolved merge conflicts.] Signed-off-by: -
Huacai Chen authored
This patch adjust the logic in mach_irq_dispatch(), allow multiple IPs handled in the same dispatching. This can speedup interrupt processing. Signed-off-by:
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Huacai Chen authored
SB700/SB710/SB800 chipset ACPI code is mostly Loongson-3 specific routines rather than a "platform driver". Signed-off-by:
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Antonio Ospite authored
Strip some comments which probably meant to repeat the same value of the define; they also contained a confusing 0x0x prefix. Signed-off-by:
Antonio Ospite <ao2@ao2.it> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12254/Signed-off-by:
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James Hogan authored
The files watch.c and ptrace.c contain various magic masks for WatchLo/WatchHi register fields. Add some definitions to mipsregs.h for these registers and make use of them in both watch.c and ptrace.c, hopefully making them more readable. Signed-off-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12729/Signed-off-by:
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James Hogan authored
do_watch() clears bit 22 of cause without using a CAUSEF_* definition from mipsregs.h. Add a definition for this bit (CAUSEF_WP) and make use of it. Also use clear_c0_cause() instead of manual read/modify/write. Signed-off-by:
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Purna Chandra Mandal authored
Adds support for the deadman timer peripheral found on PIC32 class devices. The primary function of the deadman timer (DMT) is to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in sleep mode. Signed-off-by:
Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by:
Joshua Henderson <joshua.henderson@microchip.com> Reviewed-by:
Guenter Roeck <linux@roeck-us.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12703/Signed-off-by:
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Purna Chandra Mandal authored
Document the devicetree bindings for the deadman timer peripheral found on Microchip PIC32 SoC class devices. Signed-off-by:
Rob Herring <robh@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Wim Van Sebroeck <wim@iguana.be> Cc: Guenter Roeck <linux@roeck-us.net> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-watchdog@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12702/Signed-off-by:
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Joshua Henderson authored
Add support for the watchdog peripheral found on PIC32 class devices. Signed-off-by:
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Joshua Henderson authored
Document the devicetree bindings for the watchdog peripheral found on Microchip PIC32 SoC class devices. Signed-off-by:
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Andrzej Hajda authored
IS_ERR_VALUE macro should be used only with unsigned long type. Specifically it works incorrectly with longer types. The patch follows conclusion from discussion on LKML [1][2]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2120927 [2]: http://permalink.gmane.org/gmane.linux.kernel/2150581 [ralf@linux-mips.org: While it may not immediately be obvious, the type of st_value in the end is an unsigned long equivalent so the invocation of IS_ERR_VALUE() was valid but I'm applying the patch anyway for clarity.] Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Cc: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12553/Signed-off-by:
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Maciej W. Rozycki authored
Propagate sNaN payload in quieting in the legacy-NaN mode as well. If clearing the quiet bit would produce infinity, then set the next lower trailing significand field bit, matching the SB-1 and BMIPS5000 hardware implementations. Some other MIPS FPU hardware implementations do produce the default qNaN bit pattern instead. This reverts some changes made for semantics preservation with commit dc3ddf42 [MIPS: math-emu: Update sNaN quieting handlers], consequently bringing back most of the semantics from before commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.], except from the qNaN produced in the infinity case. Previously the default qNaN bit pattern was produced in that case. Signed-off-by:
Maciej W. Rozycki <macro@imgtec.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11483/Signed-off-by:
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Maciej W. Rozycki authored
Update the ELF personality macros used for individual ABIs to make actions in the same order across all of them and match formatting too. Signed-off-by:
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James Hogan authored
Since commit 8cb48fe1 ("MIPS: Provide correct siginfo_t.si_stime"), MIPS' uapi/asm/siginfo.h has included uapi/asm-generic/siginfo.h directly before defining MIPS' struct siginfo, in order to get the necessary definitions needed for the siginfo struct without the generic copy_siginfo() hitting compiler errors due to struct siginfo not yet being defined. Now that the generic copy_siginfo() is moved out to linux/signal.h we can safely include asm-generic/siginfo.h before defining the MIPS specific struct siginfo, which avoids the uapi/ include as well as breakage due to generic copy_siginfo() being defined before struct siginfo. Reported-by:
Christopher Ferris <cferris@google.com> Fixes: 8cb48fe1 ("MIPS: Provide correct siginfo_t.si_stime") Signed-off-by:
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James Hogan authored
The generic copy_siginfo() is currently defined in asm-generic/siginfo.h, after including uapi/asm-generic/siginfo.h which defines the generic struct siginfo. However this makes it awkward for an architecture to use it if it has to define its own struct siginfo (e.g. MIPS and potentially IA64), since it means that asm-generic/siginfo.h can only be included after defining the arch-specific siginfo, which may be problematic if the arch-specific definition needs definitions from uapi/asm-generic/siginfo.h. It is possible to work around this by first including uapi/asm-generic/siginfo.h to get the constants before defining the arch-specific siginfo, and include asm-generic/siginfo.h after. However uapi headers can't be included by other uapi headers, so that first include has to be in an ifdef __kernel__, with the non __kernel__ case including the non-UAPI header instead. Instead of that mess, move the generic copy_siginfo() definition into linux/signal.h, which allows an arch-specific uapi/asm/siginfo.h to include asm-generic/siginfo.h and define the arch-specific siginfo, and for the generic copy_siginfo() to see that arch-specific definition. Signed-off-by:
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Yang Shi authored
octeon_smp_setup and octeon_prepare_cpus are just used during initialization period, so mark them as __init. And, octeon_prepare_cpus is just used in smp.c, so make it static as well. Signed-off-by:
Yang Shi <yang.shi@windriver.com> Cc: david.daney@cavium.com Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12574/Signed-off-by:
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Álvaro Fernández Rojas authored
- Remove unneeded leds0 alias. - Switch to bcm6345-l1-intc interrupt controller. - Use interrupt-controller instead of periph_intc and cpu_intc. - Add uart1 node. - Single ohci and ehci nodes. - Avoid using underscores in node names. - Rename uart aliases to serial. - Remove blank line in cpus node. [ralf@linux-mips.org: fix references in bcm96368mvwg.dts so the file keeps building.] Signed-off-by:
Álvaro Fernández Rojas <noltari@gmail.com> Cc: f.fainelli@gmail.com Cc: jogo@openwrt.org Cc: cernekee@gmail.com Cc: robh@kernel.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by:
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Álvaro Fernández Rojas authored
- Remove unneeded leds0 alias. - Switch to bcm6345-l1-intc interrupt controller. - Use interrupt-controller instead of periph_intc and cpu_intc. - Add uart1, ehci and ohci nodes. - Refactor syscon and syscon-reboot. - Avoid using underscores in node names. - Rename uart aliases to serial. Signed-off-by:
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Álvaro Fernández Rojas authored
This SoC is very similar to BCM63168 and Broadcom usually refers to them as BCM63268. Add BCM63268 and missing BCM63168 to device tree documentation. Signed-off-by:
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Álvaro Fernández Rojas authored
This adds a device tree example for SFR Neufbox4 (Sercomm version), which also serves as a real example for brcm,bcm6358-leds. Signed-off-by:
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Álvaro Fernández Rojas authored
BCM6358 has a shared TLB which conflicts with current SMP support, so it must be disabled for now. BCM6358 uses >= 0xfffe0000 addresses for internal registers, which need to be remapped (by using a simplified version of BRCM63xx ioremap.h). However, 0xfff80000 is a better address, since it also covers BCM3368, leaving the possibility to add it in the future. Signed-off-by:
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Kelvin Cheung authored
This patch replaces goto out with return in ls1x_cpufreq_probe(). Signed-off-by:
Kelvin Cheung <keguang.zhang@gmail.com> Acked-by:
Viresh Kumar <viresh.kumar@linaro.org> Cc: Rafael J. Wysocki <rjw@rjwysocki.net> Cc: linux-pm@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13056/Signed-off-by:
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Kelvin Cheung authored
This patch uses devm_kzalloc() instead of global structure. Signed-off-by:
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Kelvin Cheung authored
This patch uses dev_get_platdata() to get the platform_data instead of referencing it directly. Signed-off-by:
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Kelvin Cheung authored
This patch replaces kzalloc() with kcalloc() when allocating frequency table, and remove unnecessary 'out of memory' message. Signed-off-by:
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Kelvin Cheung authored
This patch renames the file to loongson1-cpufreq.c, and also includes some minor updates. Signed-off-by:
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Florian Fainelli authored
Just to ease debugging of multiplatform kernel, make sure we print "Broadcom BMIPS5200" for the BMIPS5200 implementation instead of Broadcom BMIPS5000. Fixes: 68e6a783 ("MIPS: BMIPS: Add PRId for BMIPS5200 (Whirlwind)") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13014/Signed-off-by:
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Florian Fainelli authored
BMIPS_GENERIC being multiplatform and intended to support BMIPS3200, BMIPS3300, BMIPS4350, BMIPS4380 and BMIPS5000-class processors, there is not much more we can put in there since they do not share the same I and D cache line sizes at all (doubled for every new generation essentially), some processors have a S-cache, some don't, some have a FPU, some don't. Signed-off-by:
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Florian Fainelli authored
local_r4k___flush_cache_all() is missing a special check for BMIPS5000 processors, we need to blast the S-cache, just like other MTI processors since we have an inclusive cache. We also need an additional __sync() to make sure this is completed. Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by:
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Florian Fainelli authored
BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is properly handled by the per-CPU override added at the end of r4k_cache_init(), the problem is that the output of probe_pcache() disagrees with that, since this is too late: Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes. Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes With the change moved earlier, we now have a consistent output with the settings we are intending to have: Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes. Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by:
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Florian Fainelli authored
BMIPS5000 and BMIPS52000 processors have their I-cache filling from the D-cache. Since BMIPS_GENERIC does not provide (yet) a cpu-feature-overrides.h file, this was not set anywhere, so make sure the R4K cache detection takes care of that. Fixes: d74b0172 ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by:
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Florian Fainelli authored
Enable CONFIG_MTD_BCM63XX_PARTS in arch/mips/configs/bmips_be_defconfig since this is a necessary option to parse the built-in flash partition table on BMIPS big-endian SoCs (Cable Modem and DSL). Signed-off-by:
Brian Norris <computersforpeace@gmail.com> Cc: cernekee@gmail.com Cc: jogo@openwrt.org Cc: simon@fire.lp0.eu Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12256/Signed-off-by:
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Florian Fainelli authored
Enable CONFIG_MTD_BCM63XX_PARTS in arch/mips/configs/bcm63xx_defconfig since this is a necessary option to parse the built-in flash partition table on BCM63xx SoCs. Signed-off-by:
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Kelvin Cheung authored
This patch adds Loongson1 architecture entry. Signed-off-by:
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Kelvin Cheung authored
- Add DMA device - Add NAND device - Add GPIO device - Add LED device - Update the defconfig and rename it to loongson1b_defconfig - Fix ioremap size - Other minor fixes Signed-off-by:
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Maciej W. Rozycki authored
... making upstream development binutils snapshots work as expected, e.g.: $ mips64el-linux-ld --version GNU ld (GNU Binutils) 2.20.1.20100303 [...] $ Signed-off-by:
Michal Marek <mmarek@suse.cz> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-kbuild@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/12537/Signed-off-by:
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