1. 01 Mar, 2017 26 commits
    • Len Brown's avatar
      tools/power turbostat: add --cpu parameter · 1ef7d21a
      Len Brown authored
      With the --cpu parameter, turbostat prints only lines
      for the specified set of CPUs:
      
      sudo ./turbostat --quiet --show Core,CPU --cpu 0,1,3..5,6-7
      	Core	CPU
      	-	-
      	0	0
      	0	4
      	1	1
      	1	5
      	2	6
      	3	3
      	3	7
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      1ef7d21a
    • Len Brown's avatar
      tools/power turbostat: print sysfs C-state stats · 41618e63
      Len Brown authored
      When turbostat shows % of time in a CPU idle power state,
      it has always been showing information from underlying
      hardware residency counters.
      
      While this reflects what the hardware is doing, and is thus
      useful for understanding the hardware,
      it doesn't directly tell us what Linux requested --
      which is useful for tuning Linux itself.
      
      Here we add columns to turbostat to show the
      Linux cpuidle sub-system statistics:
      /sys/devices/system/cpu/cpu*/cpuidle/state*/*
      
      The first group of columns are the "usage", which is the
      number of times software requested that C-state in the
      measurement interval. eg C1 below.
      
      The second group of columns are the "time", which is the percentage
      of the measurement interval time that software has requested
      the specified C-state. eg C1% below.
      
      These software counters can be compared to the underlying
      hardware residency counters (eg CPU%c1	CPU%c3	CPU%c6	CPU%c7)
      to compare what sofware requested to what the hardware delivered.
      
      These sysfs attributes are discovered when turbostat starts,
      rather than being "built in".  So the --show and --hide
      parameters do not know about these dynamic column names.
      However "--show sysfs" and "--hide sysfs" act on the
      entire group of columns:
      
      turbostat --show sysfs
      ...
      cpu4: POLL: CPUIDLE CORE POLL IDLE
      cpu4: C1: MWAIT 0x00
      cpu4: C1E: MWAIT 0x01
      cpu4: C3: MWAIT 0x10
      cpu4: C6: MWAIT 0x20
      cpu4: C7s: MWAIT 0x32
      ...
      C1 	C1E	C3 	C6 	C7s	C1% 	C1E%	C3%	C6% 	C7s%
      3	6	5	1	188	0.00	0.02	0.00	0.00	99.93
      0	6	5	0	58	0.00	0.16	0.02	0.00	99.70
      0	0	0	0	9	0.00	0.00	0.00	0.00	99.96
      0	0	0	1	24	0.00	0.00	0.00	0.02	99.93
      0	0	0	0	9	0.00	0.00	0.00	0.00	99.97
      0	0	0	0	32	0.00	0.00	0.00	0.00	99.96
      0	0	0	0	7	0.00	0.00	0.00	0.00	99.98
      2	0	0	0	36	0.00	0.00	0.00	0.00	99.97
      1	0	0	0	13	0.00	0.00	0.00	0.00	99.98
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      41618e63
    • Len Brown's avatar
      tools/power turbostat: extend --add option to accept /sys path · 495c7654
      Len Brown authored
      Previously, the --add option could specify only an MSR.
      
      Here is is extended so an arbitrary /sys attribute,
      as specified by an absolute file path name.
      
      sudo ./turbostat --add /sys/devices/system/cpu/cpu0/cpuidle/state5/usage
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      495c7654
    • Len Brown's avatar
      tools/power turbostat: skip unused counters on BDX · ade0ebac
      Len Brown authored
      Skip these two counters on BDX, as they are always zero:
      cc7, pc7
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      ade0ebac
    • Len Brown's avatar
      tools/power turbostat: fix decoding for GLM, DNV, SKX turbo-ratio limits · 31e07522
      Len Brown authored
      Newer processors do not hard-code the the number of cpus in each bin
      to {1, 2, 3, 4, 5, 6, 7, 8}  Rather, they can specify any number
      of CPUS in each of the 8 bins:
      
      eg.
      
      ...
      37 * 100.0 = 3600.0 MHz max turbo 4 active cores
      38 * 100.0 = 3700.0 MHz max turbo 3 active cores
      39 * 100.0 = 3800.0 MHz max turbo 2 active cores
      39 * 100.0 = 3900.0 MHz max turbo 1 active cores
      
      could now look something like this:
      
      ...
      37 * 100.0 = 3600.0 MHz max turbo 16 active cores
      38 * 100.0 = 3700.0 MHz max turbo 8 active cores
      39 * 100.0 = 3800.0 MHz max turbo 4 active cores
      39 * 100.0 = 3900.0 MHz max turbo 2 active cores
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      31e07522
    • Len Brown's avatar
      tools/power turbostat: skip unused counters on SKX · 34c76197
      Len Brown authored
      Skip these four counters on SKX, as they are always zero:
      cc3, pc3
      cc7, pc7
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      34c76197
    • Len Brown's avatar
      tools/power turbostat: Denverton: use HW CC1 counter, skip C3, C7 · 7170a374
      Len Brown authored
      The CC1 column in tubostat can be computed by subtracting
      the core c-state residency countes from the total Cx residency.
      
      CC1 = (Idle_time_as_measured by MPERF) - (all core C-states with
      residency counters)
      
      However, as the underlying counter reads are not atomic,
      error can be noticed in this calculations, especially
      when the numbers are small.
      
      Denverton has a hardware CC1 residency counter
      to improve the accuracy of the cc1 statistic -- use it.
      
      At the same time, Denverton has no concept of CC3, PC3, CC7, PC7,
      so skip collecting and printing those columns.
      
      Finally, a note of clarification.
      Turbostat prints the standard PC2 residency counter,
      but on Denverton hardware, that actually means PC1E.
      Turbostat prints the standard PC6 residency counter,
      but on Denverton hardware, that actually means PC2.
      
      At this point, we document that differnce in this commit message,
      rather than adding a quirk to the software.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      7170a374
    • Len Brown's avatar
      tools/power turbostat: initial Gemini Lake SOC support · ac01ac13
      Len Brown authored
      Gemini Lake is similar to Apollo Lake (Broxton/Goldmont)
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      ac01ac13
    • Len Brown's avatar
      x86: intel-family.h: Add GEMINI_LAKE SOC · 311f7770
      Len Brown authored
      Cc: x86@kernel.org
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      311f7770
    • Len Brown's avatar
      tools/power turbostat: bug fixes to --add, --show/--hide features · 0f47c08d
      Len Brown authored
      Fix a bug with --add, where the title of the column
      is un-initialized if not specified by the user.
      
      The initial implementation of --show and --hide
      neglected to handle the pc8/pc9/pc10 counters.
      
      Fix a bug where "--show Core" only worked with --debug
      Reported-by: default avatarWendy Wang <wendy.wang@intel.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      0f47c08d
    • Len Brown's avatar
      tools/power turbostat: use tsc_tweak everwhere it is needed · 008d396e
      Len Brown authored
      The CPU ticks at a rate in the "bus clock" domain.
      eg. 100 MHz * bus_ratio.
      
      On newer processors, the TSC has been moved out of this BCLK
      domain and into a separate crystal-clock domain.
      
      While the TSC ticks "close to" the base frequency, those that look
      closely at the numbers will notice small errors in calculations that
      mix units of TSC clocks and bus clocks.
      
      "tsc_tweak" was introduced to address the most visible
      mixing -- the %Busy and the the Busy_MHz calculations.
      (A simplification as since removed TSC from the BusyMHz calculation)
      
      Here we apply the tsc_tweak to everyplace where BCLK
      and TSC units are mixed.  The results is that
      on a system which is 100% idle, the sum of the C-states
      are now much more likely to be closer to 100%.
      Reported-by: default avatarTravis Downs <travis.downs@gmail.com>
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      008d396e
    • Len Brown's avatar
      tools/power turbostat: print system config, unless --quiet · 96e47158
      Len Brown authored
      Some users want turbostat to tell them everything, by default.
      Some users want turbostat to be quiet, by default.
      
      I find that I'm in the 1st camp, and so I've never liked
      needing to type the --debug parameter to decode the system
      configuration.
      
      So here we change the default and print the system configuration,
      by default.  (The --debug option is now un-documented, though
      it does still exist for debugging turbostat internals)
      
      When you do not want to see the system configuration
      header, use the new "--quiet" option.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      96e47158
    • Len Brown's avatar
      tools/power turbostat: show all columns, independent of --debug · fee86541
      Len Brown authored
      Some time ago, turbostat overflowed 80 columns.
      
      So on the assumption that a "casual" user would always
      want topology and frequency columns, we hid the rest
      of the columns and the system configuration decoding
      behind the --debug option.
      
      Not everybody liked that change -- including me.
      I use --debug 99% of the time...
      
      Well, now we have "-o file" to put turbostat output into a file,
      so unless you are watching real-time in a small window,
      column count is less frequently a factor.
      
      And more recently, we got the "--hide columnA,columnB" option
      to specify columns to skip.
      
      So now we "un-hide" the rest of the columns from behind --debug,
      and show them all, by default.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      fee86541
    • Len Brown's avatar
      tools/power turbostat: decode MSR_MISC_FEATURE_CONTROL · 33148d67
      Len Brown authored
      useful for observing if the BIOS disabled prefetch
      Not architectural, but docuemented as present on NHM, SNB
      and is present on others.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      33148d67
    • Len Brown's avatar
      x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL · 98af7459
      Len Brown authored
      This non-architectural MSR has disable bits
      for various prefetchers on modern processors.
      
      While these bits are generally touched only by the BIOS,
      say, via BIOS SETUP, it is useful to dump them
      when examining options that can alter performance.
      
      Cc: x86@kernel.org
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      98af7459
    • Len Brown's avatar
      tools/power turbostat: decode CPUID(6).TURBO · b3a34e93
      Len Brown authored
      show the CPUID feature for turbo to clarify the case
      when it may not be shown in MISC_ENABLE
      
      CPUID(6): APERF, TURBO, DTS, PTM, No-HWP, No-HWPnotify, No-HWPwindow, No-HWPepp, No-HWPpkg, EPB
      cpu4: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      b3a34e93
    • Len Brown's avatar
      tools/power turbostat: dump Atom P-states correctly · 0f7887c4
      Len Brown authored
      Turbostat dumps MSR_TURBO_RATIO_LIMIT on Core Architecture.
      But Atom Architecture uses MSR_ATOM_CORE_RATIOS and
      MSR_ATOM_CORE_TURBO_RATIOS.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      0f7887c4
    • Len Brown's avatar
      intel_pstate: use MSR_ATOM_RATIOS definitions from msr-index.h · 92134bdb
      Len Brown authored
      Originally, these MSRs were locally defined in this driver.
      Now the definitions are in msr-index.h -- use them.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      92134bdb
    • Len Brown's avatar
      x86 msr-index.h: Define Atom specific core ratio MSR locations · 8a34fd02
      Len Brown authored
      These MSRs are currently used by the intel_pstate driver,
      using a local definition.
      
      Cc: x86@kernel.org
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      8a34fd02
    • Len Brown's avatar
      tools/power turbostat: further decode MSR_IA32_MISC_ENABLE · e6512624
      Len Brown authored
      Decode MISC_ENABLE.NO_TURBO,
      also use the #defines in msr-index.h for decoding this register
      
      cpu0: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST MWAIT TURBO)
      
      Although it is not architectural, decode also
      MSR_IA32_MISC_ENABLE.prefetch-disable (bit-9).
      documented to be present on: Core, P4, Intel-Xeon
      reserved on: Atom, Silvermont, Nehalem, SNB, PHI ec.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      e6512624
    • Len Brown's avatar
      tools/power turbostat: add precision to --debug frequency output · 710f273b
      Len Brown authored
      Add a digit of precision to the --debug output for frequency range.
      This is useful when BCLK is not an integer.
      
      old:
      6 * 83 = 500 MHz max efficiency frequency
      26 * 83 = 2166 MHz base frequency
      
      new:
      6 * 83.3 = 499.8 MHz max efficiency frequency
      26 * 83.3 = 2165.8 MHz base frequency
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      710f273b
    • Len Brown's avatar
      tools/power turbostat: Baytrail c-state support · 0539ba11
      Len Brown authored
      The Baytrail SOC, with its Silvermont core, has some unique properties:
      
      1. a hardware CC1 residency counter
      2. a module-c6 residency counter
      3. a package-c6 counter at traditional package-c7 counter address.
      
      The SOC does not support c3, pc3, c7 or pc7 counters.
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      0539ba11
    • Len Brown's avatar
      x86: msr-index.h: Remove unused MSR_NHM_SNB_PKG_CST_CFG_CTL · 419c9e98
      Len Brown authored
      The two users, intel_idle driver and turbostat utility
      are using the new name, MSR_PKG_CST_CONFIG_CONTROL
      
      Cc: x86@kernel.org
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      419c9e98
    • Len Brown's avatar
      tools/power turbostat: use new name for MSR_PKG_CST_CONFIG_CONTROL · 1df2e55a
      Len Brown authored
      Previously called MSR_NHM_SNB_PKG_CST_CFG_CTL
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      1df2e55a
    • Len Brown's avatar
      intel_idle: use new name for MSR_PKG_CST_CONFIG_CONTROL · 6cfb2374
      Len Brown authored
      previously known as  MSR_NHM_SNB_PKG_CST_CFG_CTL
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      6cfb2374
    • Len Brown's avatar
      x86: msr-index.h: Define MSR_PKG_CST_CONFIG_CONTROL · 40496c8e
      Len Brown authored
      define MSR_PKG_CST_CONFIG_CONTROL (0xE2),
      which is the string used by Intel Documentation.
      
      We use this MSR in intel_idle and turbostat by a previous name,
      to be updated in the next patch.
      
      Cc: x86@kernel.org
      Signed-off-by: default avatarLen Brown <len.brown@intel.com>
      40496c8e
  2. 25 Feb, 2017 6 commits
  3. 19 Feb, 2017 8 commits