- 10 Mar, 2022 14 commits
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Ville Syrjälä authored
Grab the DRRS MSA timing delay value from the VBT and program things accordingly. Only ilk/snb/ivb have this so presumably on hsw+ we don't need it. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220310004802.16310-6-ville.syrjala@linux.intel.comReviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Ville Syrjälä authored
VBT hsa a field for the MSA timing delay, which supposedly should be used with DRRS. Extract the data from the VBT. Signed-off-by:
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Ville Syrjälä authored
Use the standard [CONNECTOR:%d:%s] format in the DRRS debugs. Signed-off-by:
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Ville Syrjälä authored
Pass the fixed_mode as const to intel_drrs_init() since it's not supposed to mutate the mode. Signed-off-by:
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Ville Syrjälä authored
Only seamless DRRS needs the frontbuffer tracking, so check for that. Also use != consistently instead of randomly picking < as the comparison operator. Signed-off-by:
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Ville Syrjälä authored
struct dp_link_dpll is a pointless wrapper around struct dpll. Just store the desired link rate into struct dpll::dot and we're done. v2: Document the full divider as a proper decimal number on chv Nuke bogus eDP 1.4 comments for chv while at it Signed-off-by: -
Ville Syrjälä authored
Set the bxt/glk DPLL min dotclock to 25MHz (HDMI minimum) and the max to 594 MHz (HDMI max). The supported DP frequencies (162MHz-540MHz) fit within the same range. Signed-off-by:
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Ville Syrjälä authored
Use chv_calc_dpll_params() to calculate the BXT DP DPLL VCO frequency. We need to add the m1 divider into bxt_dp_clk_val[] for this to work. v2: Make the WARN_ON() sensible Signed-off-by:
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Ville Syrjälä authored
bxt_clk_div is basically the same as struct dpll. Just use the latter. Reviewed-by:
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Ville Syrjälä authored
Get rid of the pointless m2 int vs. frac split in bxt_clk_div and just store the whole divider as one. v2: Document the full divider as a proper decimal number Signed-off-by:
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Ville Syrjälä authored
Use REG_BIT() & co. for bxt/glk PLL registers. v2: Reorder a few bits for consistency Signed-off-by:
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Ville Syrjälä authored
Remove the comment specifying the exact formulat for calculating the DPLL frequency from the *_find_best_dpll() functions. Each platform variant has its own way to calculate these and we have the code already to do that. These comments are entirely redundant and often even wrong so just get rid of them. Signed-off-by:
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Ville Syrjälä authored
Unify vlv/chv with earlier platforms so that the sturct dpll::dot represents the /5 clock frequency (ie. DP symbol rate or HDMI TMDS rate) rather than the *5 fast clock (/2 of the bitrate). Makes life a little less confusing to get the same number back in .dot which we fed into the DPLL algorithm. v2: Actually just include the 5x in the final P divider Do the same change to the hand rolled gvt code v3: Missed a few *5 in *_find_best_dpll() Reviewed-by: -
Ville Syrjälä authored
When using bigjoiner it's useful to know the offset of each individual pipe in the whole set of joined pipes. Let's include that information in our PIPESRC rectangle. With this we can make the plane clipping code blissfully unaware of bigjoiner usage, as all we have to do is remove the pipe's offset from the final plane destination coordinates. v2: Use intel_bigjoiner_num_pipes() Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com>
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- 09 Mar, 2022 2 commits
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Ville Syrjälä authored
GLK doesn't support SAGV, so with CNL gone there is no use for having a DISPLAY_VER==10 SAGV block time in the code. Signed-off-by:
Vinod Govindapillai <vinod.govindapillai@intel.com>
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Changcheng Deng authored
Use min_t() in order to make code cleaner. Reported-by:
Zeal Robot <zealci@zte.com.cn> Signed-off-by:
Changcheng Deng <deng.changcheng@zte.com.cn> Signed-off-by:
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- 07 Mar, 2022 2 commits
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Jani Nikula authored
We have a helper for getting at the enclosing gmbus struct from the embedded i2c_adapter, use it. Signed-off-by:
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Jani Nikula authored
Limit the scope. Suggested-by:
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- 04 Mar, 2022 19 commits
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Ville Syrjälä authored
Replace the hardcoded 2 pipe assumptions when we're massaging pipe_mode and the pipe_src rect to be suitable for bigjoiner. Instead we can just count the number of pipes in the bitmask. v2: Introduce intel_bigjoiner_num_pipes() Signed-off-by:
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Ville Syrjälä authored
Since we now have the bigjoiner_pipes bitmask the boolean is redundant. Get rid of it. Also, populating bigjoiner_pipes already during encoder->compute_config() allows us to use it much earlier during the state calculation as well. The initial aim is to use it in intel_crtc_compute_config(). v2: Move the hweight(bigjoiner_pipes) stuff to a later patch Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com> #v1 Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> #v1 Signed-off-by:
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Ville Syrjälä authored
Instead of just having the pipe_src_{w,h} let's use a full drm_rect for it. This will be particularly useful to astract away some bigjoiner details. v2: No hweight() stuff yet Signed-off-by: -
Ville Syrjälä authored
Use designated initializers to make it clear what is what, and to decouple us from the specific ordering of the members. Signed-off-by:
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Ville Syrjälä authored
Remove the pointless m2_frac_en from bxt_clk_div. Signed-off-by:
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Ville Syrjälä authored
Use the simple '= {}' form to initialize empty arrays/structs. Also add some missing whitespace. Signed-off-by: -
Ville Syrjälä authored
Toss a bunch if constants into .rodata drom the stack. Also shrink the types of some of the arrays to reduce the size. bloat-o-meter -c intel_dpll_mgr.o: add/remove: 0/0 grow/shrink: 0/2 up/down: 0/-86 (-86) Function old new delta icl_get_dplls 3393 3372 -21 skl_get_dpll 2069 2004 -65 Total: Before=28029, After=27943, chg -0.31% add/remove: 0/0 grow/shrink: 0/0 up/down: 0/0 (0) Data old new delta Total: Before=17, After=17, chg +0.00% add/remove: 2/0 grow/shrink: 0/2 up/down: 28/-129 (-101) RO Data old new delta dco_central_freq - 24 +24 div1_vals - 4 +4 odd_dividers 28 7 -21 even_dividers 144 36 -108 Total: Before=3600, After=3499, chg -2.81% Signed-off-by:
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Ville Syrjälä authored
We can trivially replace skl_wrpll_context_init() with a single designated initializer. Signed-off-by:
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Ville Syrjälä authored
Move intel_crtc_pch_transcoder() and has_pch_trancoder() to a more appropritate place (intel_pch_display.c). Signed-off-by:
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Ville Syrjälä authored
Move the ibx pch port sanitation code into intel_pch_display.c where it now belongs. Signed-off-by:
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Ville Syrjälä authored
Now that we track framestart_delay in the crtc state with readout and state checker support we can remove the explicit framestart_delay sanitation code. Also I'm not convinced reprogramming this while the pipe is running is even valid. CHICKEN_TRANS (hsw+) and TRANS_CHICKEN2 (cpt+) docs at least make no mention of double buffering which seems to imply that live reprogramming is not supported. On older platforms PIPECONF and PCH_TRANSCONF (ibx) are double buffered though, so might be that we could do this on the older platforms. But doesn't really make sense to special case old platforms for this. So from now on if the BIOS has misprogrammed this we shall simply do a full modeset at boot to fix it up. Such systems will of course lose fastboot, but I think less code (and less uncertainty what reprogramming this on a running pipe will even do) outweighs that. Signed-off-by:
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Ville Syrjälä authored
We need to make framestart_delay dynamic for DRRS on PCH ports. To that end move it into the crtc state. As a bonus we get state check+dump for it. Will also allow us to get rid of the somewhat questionable framestart_delay sanitation code. Signed-off-by:
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Madhumitha Tolakanahalli Pradeep authored
Changes since v2.14: - Release Notes for v2.15 Fix for corruption issue when DC States are enabled. - Release Notes for v2.16 Fix for cases with flip queue and DC6v are enabled. Signed-off-by:
Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220223222801.397632-2-madhumitha.tolakanahalli.pradeep@intel.com
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Jani Nikula authored
Include linux/highmem.h and linux/swap.h explicitly where needed so we can drop the linux/i2c.h include from i915_drv.h where it pulled in the dependencies implicitly. Signed-off-by:
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Jani Nikula authored
Allocate the individual intel_gmbus structs dynamically. This lets us hide struct intel_gmbus inside intel_gmbus.c completely. Also use the cleanup function on the error path to avoid duplication. Leave #include <linux/i2c.h> in i915_drv.h for now, as it pulls in a bunch of implicit dependencies. Signed-off-by:
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Jani Nikula authored
Avoid the additional gmbus lookup on the pin. Signed-off-by:
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Jani Nikula authored
Avoid separate pin lookups for validity and name. Signed-off-by:
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Jani Nikula authored
Combine the platform specific if ladders for array lookup and size checks into one. This is cleaner and avoids duplication, but hopefully also helps any static analyzers that seem to have trouble with the bounds checks. Signed-off-by:
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Tejas Upadhyay authored
Add ADL-N stepping-substepping info in accordance to BSpec. Bspec: 68397 Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by:
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- 03 Mar, 2022 3 commits
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Ville Syrjälä authored
Print the offending plane/crtc id+name in the async flip debugs. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Signed-off-by:
Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
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Ville Syrjälä authored
The current implementation of the async flip wm0/ddb optimization does not work at all. The biggest problem is that we skip the whole intel_pipe_update_{start,end}() dance and thus never actually complete the commit that is trying to do the wm/ddb change. To fix this we need to move the do_async_flip flag to the crtc state since we handle commits per-pipe, not per-plane. Also since all planes can now be included in the first/last "async flip" (which gets converted to a sync flip to do the wm/ddb mangling) we need to be more careful when checking if the plane state is async flip comptatible. Only planes doing the async flip should be checked and other planes are perfectly fine not adhereing to any async flip related limitations. However for subsequent commits which are actually going do the async flip in hardware we want to make sure no other planes are in the state. That should never happen assuming we did our job correctly, so we'll toss in a WARN to make sure we catch any bugs here. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by: -
Ville Syrjälä authored
Since the async flip state check is done very late and thus it can see potentially all the planes in the state (due to the wm/ddb optimization) we need to move the "can the requested plane do async flips at all?" check much earlier. For this purpose we introduce intel_async_flip_check_uapi() that gets called early during the atomic check. And for good measure we'll throw in a couple of basic checks: - is the crtc active? - was a modeset flagged? - is+was the plane enabled? Though atm all of those should be guaranteed by the fact that the async flip can only be requested through the legacy page flip ioctl. Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> Fixes: c3639f3b ("drm/i915: Use wm0 only during async flips for DG2") Signed-off-by:
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