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  1. 19 Feb, 2017 10 commits
  3. 16 Feb, 2017 3 commits
  5. 14 Feb, 2017 3 commits
  7. 13 Feb, 2017 1 commit
  9. 09 Feb, 2017 1 commit
  11. 31 Jan, 2017 4 commits
    • Kamal Dasu's avatar
      spi: bcm-qspi: Added mspi read fallback in bcm_qspi_flash_read() · 81ab52fd
      Kamal Dasu authored 
      Added mspi read fallback under certain circumstances like unaligned
buffer, address on short reads. Also takes care of version 3.0 spi
controller where flash address crosses 4MB boundary on transfers the
driver resorts to mspi reads.
Signed-off-by: default avatarKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      81ab52fd
    • Johan Hovold's avatar
      spi: fix device-node leaks · 8324147f
      Johan Hovold authored 
      Make sure to release the device-node reference taken in
of_register_spi_device() on errors and when deregistering the device.

Fixes: 284b0189 ("spi: Add OF binding support for SPI busses")
Signed-off-by: default avatarJohan Hovold <johan@kernel.org>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      8324147f
    • Daniel Kurtz's avatar
      spi: mediatek: Only do dma for 4-byte aligned buffers · 1ce24864
      Daniel Kurtz authored 
      Mediatek SPI DMA only works when tx and rx buffer addresses are 4-byte
aligned.

Unaligned DMA transactions appeared to work previously, since we the
spi core was incorrectly using the spi_master device for dma, which
had a 0 dma_mask, and therefore the swiotlb dma map operations were
falling back to using bounce buffers.  Since each DMA transaction would
use its own buffer, the mapped starting address of each transaction was
always aligned.  When doing real DMA, the mapped address will share the
alignment of the raw tx/rx buffer provided by the SPI user, which may or
may not be aligned.

If a buffer is not aligned, we cannot use DMA, and must use FIFO based
transaction instead.

So, this patch implements a scheme that allows using the FIFO for
arbitrary length transactions (larger than the 32-byte FIFO size) by
reloading the FIFO in the interrupt handler.
Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Cc: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      1ce24864
    • Daniel Kurtz's avatar
      spi: When no dma_chan map buffers with spi_master's parent · 88b0aa54
      Daniel Kurtz authored 
      Back before commit 1dccb598 ("arm64: simplify dma_get_ops"), for
arm64, devices for which dma_ops were not explicitly set were automatically
configured to use swiotlb_dma_ops, since this was hard-coded as the
global "dma_ops" in arm64_dma_init().

Now that global "dma_ops" has been removed, all devices much have their
dma_ops explicitly set by a call to arch_setup_dma_ops(), otherwise the
device is assigned dummy_dma_ops, and thus calls to map_sg for such a
device will fail (return 0).

Mediatek SPI uses DMA but does not use a dma channel.  Support for this
was added by commit c37f45b5 ("spi: support spi without dma channel
to use can_dma()"), which uses the master_spi dev to DMA map buffers.

The master_spi device is not a platform device, rather it is created
in spi_alloc_device(), and therefore its dma_ops are never set.

Therefore, when the mediatek SPI driver when it does DMA (for large SPI
transactions > 32 bytes), SPI will use spi_map_buf()->dma_map_sg() to
map the buffer for use in DMA.  But dma_map_sg()->dma_map_sg_attrs() returns
0, because ops->map_sg is dummy_dma_ops->__dummy_map_sg, and hence
spi_map_buf() returns -ENOMEM (-12).

Fix this by using the real spi_master's parent device which should be a
real physical device with DMA properties.
Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
Fixes: c37f45b5 ("spi: support spi without dma channel to use can_dma()")
Cc: Leilk Liu <leilk.liu@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
      88b0aa54
  13. 23 Jan, 2017 2 commits
  15. 19 Jan, 2017 1 commit
  17. 17 Jan, 2017 11 commits
  19. 12 Jan, 2017 1 commit
  21. 10 Jan, 2017 1 commit
  23. 09 Jan, 2017 2 commits
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