1. 18 Feb, 2021 30 commits
  2. 17 Feb, 2021 7 commits
  3. 16 Feb, 2021 3 commits
    • Arnaldo Carvalho de Melo's avatar
      37b3fa0e
    • Arnaldo Carvalho de Melo's avatar
      Merge branch 'perf/urgent' into perf/core · c1bd8a2b
      Arnaldo Carvalho de Melo authored
      To get some fixes that didn't made into 5.11.
      Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
      c1bd8a2b
    • Leo Yan's avatar
      perf arm-spe: Set sample's data source field · a89dbc9b
      Leo Yan authored
      The sample structure contains the field 'data_src' which is used to
      tell the data operation attributions, e.g. operation type is loading or
      storing, cache level, it's snooping or remote accessing, etc.  At the
      end, the 'data_src' will be parsed by perf mem/c2c tools to display
      human readable strings.
      
      This patch is to fill the 'data_src' field in the synthesized samples
      base on different types.  Currently perf tool can display statistics for
      L1/L2/L3 caches but it doesn't support the 'last level cache'.  To fit
      to current implementation, 'data_src' field uses L3 cache for last level
      cache.
      
      Before this commit, perf mem report looks like this:
        # Samples: 75K of event 'l1d-miss'
        # Total weight : 75951
        # Sort order   : local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked
        #
        # Overhead  Samples  Local Weight  Memory access  Symbol                  Shared Object  Data Symbol             Data Object  Snoop  TLB access
        # ........  .......  ............  .............  ......................  .............  ......................  ...........  .....  ..........
        #
            81.56%    61945  0             N/A            [.] 0x00000000000009d8  serial_c       [.] 0000000000000000    [unknown]    N/A    N/A
            18.44%    14003  0             N/A            [.] 0x0000000000000828  serial_c       [.] 0000000000000000    [unknown]    N/A    N/A
      
      Now on a system with Arm SPE, addresses and access types are displayed:
      
        # Samples: 75K of event 'l1d-miss'
        # Total weight : 75951
        # Sort order   : local_weight,mem,sym,dso,symbol_daddr,dso_daddr,snoop,tlb,locked
        #
        # Overhead  Samples  Local Weight  Memory access  Symbol                  Shared Object  Data Symbol             Data Object  Snoop  TLB access
        # ........  .......  ............  .............  ......................  .............  ......................  ...........  .....  ..........
        #
             0.43%      324  0             L1 miss        [.] 0x00000000000009d8  serial_c       [.] 0x0000ffff80794e00  anon         N/A    Walker hit
             0.42%      322  0             L1 miss        [.] 0x00000000000009d8  serial_c       [.] 0x0000ffff80794580  anon         N/A    Walker hit
      Signed-off-by: default avatarLeo Yan <leo.yan@linaro.org>
      Reviewed-by: default avatarJames Clark <james.clark@arm.com>
      Tested-by: default avatarJames Clark <james.clark@arm.com>
      Cc: Adrian Hunter <adrian.hunter@intel.com>
      Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
      Cc: Al Grant <al.grant@arm.com>
      Cc: Andre Przywara <andre.przywara@arm.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Cc: John Garry <john.garry@huawei.com>
      Cc: Mark Rutland <mark.rutland@arm.com>
      Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
      Cc: Namhyung Kim <namhyung@kernel.org>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Wei Li <liwei391@huawei.com>
      Cc: Will Deacon <will@kernel.org>
      Signed-off-by: default avatarJames Clark <james.clark@arm.com>
      Link: https://lore.kernel.org/r/20210211133856.2137-6-james.clark@arm.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
      a89dbc9b