- 25 Oct, 2016 40 commits
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Alex Deucher authored
Add the proper IP module when requested. Signed-off-by:Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Returns the vce clock table for the user mode driver. The user mode driver can fill this data into vce clock data packet for optimal VCE DPM. v2: update to the new API Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Used by the powerplay dpm code. v2: update to the new API v3: drop old include Reviewed-by:
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Alex Deucher authored
Used by the non-powerplay dpm code. v2: update to the new API Reviewed-by:
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Alex Deucher authored
Will be used by the new info ioctl query. v2: fetch a single state per request Reviewed-by:
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Alex Deucher authored
This is needed to set up the vce clock table in userspace for proper VCE DPM. v2: fix copy paste typo in comment v3: track number of valid states Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Alex Deucher authored
No intended functional change. Reviewed-by:
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Christian König authored
They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by:
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Christian König authored
It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by:
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Christian König authored
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by:
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Christian König authored
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by:
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Christian König authored
With the padding raised to 256 DW that shouldn't be needed any more. v2: reduce estimation as well Signed-off-by:
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Christian König authored
If a ring doesn't support that it shouldn't implement the function. Signed-off-by:
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Christian König authored
The same as on windows to avoid further problems with CE/DE command submission overlaps. Signed-off-by:
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Alex Deucher authored
Update the comment to explain why we do this. Reviewed-by:
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Alex Deucher authored
Update the comment to explain why we do this. Reviewed-by:
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Alex Deucher authored
Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by:
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Alex Deucher authored
Simplify the code and properly set the csb for harvest values. Reviewed-by:
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Alex Deucher authored
Needed when for SR-IOV and when PG is enabled. Reviewed-by:
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Alex Deucher authored
We need to cache some additional values to handle SR-IOV and PG. Reviewed-by:
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Christian König authored
Instead of messing with the PD directly. Signed-off-by:
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Christian König authored
Only cleanup, no intended functional change. Signed-off-by:
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Christian König authored
Only cleanup, no intended functional change. Signed-off-by:
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Christian König authored
Only cleanup, no intended functional change. Signed-off-by:
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Christian König authored
Saves us a bit of memory. Signed-off-by:
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Christian König authored
Saves a bunch of CPU cycles when swapping things back in and allows us to split the VM headers into a separate file. v2: rename parameters Signed-off-by:
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Christian König authored
It's completely pointless to have two pointers to the device in the same structure. v2: rename function to amdgpu_ttm_adev, fix typos Signed-off-by:
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Tom St Denis authored
Tested by reading tile/clk bits during load/idle. Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
This patch enables detecting VCE/UVD PG features and fixes the UVD powergate function. Tested on a Tonga (by reading UVD tile/clk bits during playback/idle). Signed-off-by:
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Christian König authored
Far less CPU cycles needed for this approach. v2: fix typo Signed-off-by:
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Frank Min authored
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling. Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Monk Liu authored
we found some MEC ucode leads to IB test fail or even ring test fail if Jump Table of it is not start in FW bo with page aligned address, fixed by always make JT address page aligned. we don't need to patch JT2 for MEC2, because for VI, MEC2 is a copy of MEC1, thus when converting fw_type for MEC_JT2 we just return MEC1,hw can use the same JT for both MEC1 & MEC2. above two change fixed some ring/ib test failure issue for some version of MEC ucode. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
for sriov, SMC need MEC_STORAGE reserved in fw bo. Signed-off-by:
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Frank Min authored
Signed-off-by:
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Frank Min authored
for GTT memory SMC can only access it within PF space, which is not used for SRIOV case, thus for SRIOV case, we let SMC use FB space for ucode bo. Signed-off-by:
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Frank Min authored
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Monk Liu authored
for VI smc, index_0 to index_8 are all not safe, they may used by BIOS/FW, and index_11 is reserved only for driver. Signed-off-by:
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Frank Min authored
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