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  1. 04 Nov, 2010 1 commit
    • Paul Mundt's avatar
      sh: nommu: use 32-bit phys mode. · e2fcf74f
      Paul Mundt authored
      The nommu code has regressed somewhat in that 29BIT gets set for the
      SH-2/2A configs regardless of the fact that they are really 32BIT sans
      MMU or PMB. This does a bit of tidying to get nommu properly selecting
      32BIT as it was before.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      e2fcf74f
  2. 27 Oct, 2010 1 commit
  3. 26 Oct, 2010 1 commit
  4. 18 Oct, 2010 1 commit
    • Peter Zijlstra's avatar
      irq_work: Add generic hardirq context callbacks · e360adbe
      Peter Zijlstra authored
      Provide a mechanism that allows running code in IRQ context. It is
      most useful for NMI code that needs to interact with the rest of the
      system -- like wakeup a task to drain buffers.
      
      Perf currently has such a mechanism, so extract that and provide it as
      a generic feature, independent of perf so that others may also
      benefit.
      
      The IRQ context callback is generated through self-IPIs where
      possible, or on architectures like powerpc the decrementer (the
      built-in timer facility) is set to generate an interrupt immediately.
      
      Architectures that don't have anything like this get to do with a
      callback from the timer tick. These architectures can call
      irq_work_run() at the tail of any IRQ handlers that might enqueue such
      work (like the perf IRQ handler) to avoid undue latencies in
      processing the work.
      Signed-off-by: default avatarPeter Zijlstra <a.p.zijlstra@chello.nl>
      Acked-by: default avatarKyle McMartin <kyle@mcmartin.ca>
      Acked-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
      [ various fixes ]
      Signed-off-by: default avatarHuang Ying <ying.huang@intel.com>
      LKML-Reference: <1287036094.7768.291.camel@yhuang-dev>
      Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
      e360adbe
  5. 11 Oct, 2010 1 commit
  6. 02 Oct, 2010 1 commit
  7. 01 Oct, 2010 1 commit
  8. 20 Sep, 2010 1 commit
  9. 16 Aug, 2010 1 commit
    • Sam Ravnborg's avatar
      sh: fix recursive dependency in Kconfig · e583d6b3
      Sam Ravnborg authored
      When executing:
      
         make ARCH=sh defconfig
      
      kconfig segfaulted.
      kconfig should obviously not segfault.
      
      But this indicated a problem in the sh files which was
      tracked down to a recursive dependency.
      
      We select HAVE_HW_BREAKPOINT and in the following line
      we use the same symbol in an expression.
      Drop the conditional as it is of no use.
      Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
      Cc: Michal Marek <mmarek@suse.cz>
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      e583d6b3
  10. 27 Jul, 2010 1 commit
  11. 14 Jul, 2010 1 commit
  12. 06 Jul, 2010 1 commit
  13. 14 Jun, 2010 1 commit
  14. 02 Jun, 2010 1 commit
    • Paul Mundt's avatar
      sh: support for platforms without PIO. · 86e4dd5a
      Paul Mundt authored
      This extends some of the existing special casing for HAS_IOPORT
      platforms and gets it to the point where platforms can begin to
      conditionally select it.
      
      The major changes here are that the PIO routines themselves go away
      completely, including all of the machvec port mapping wrappers. With this
      in place it's possible for any non-machvec abusing platform to disable
      PIO completely. At present this is left as an opt-in until the abusers
      are the odd ones out instead of the majority.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      86e4dd5a
  15. 31 May, 2010 1 commit
  16. 27 May, 2010 1 commit
  17. 11 May, 2010 1 commit
  18. 07 May, 2010 1 commit
  19. 01 May, 2010 1 commit
    • Frederic Weisbecker's avatar
      hw-breakpoints: Separate constraint space for data and instruction breakpoints · 0102752e
      Frederic Weisbecker authored
      There are two outstanding fashions for archs to implement hardware
      breakpoints.
      
      The first is to separate breakpoint address pattern definition
      space between data and instruction breakpoints. We then have
      typically distinct instruction address breakpoint registers
      and data address breakpoint registers, delivered with
      separate control registers for data and instruction breakpoints
      as well. This is the case of PowerPc and ARM for example.
      
      The second consists in having merged breakpoint address space
      definition between data and instruction breakpoint. Address
      registers can host either instruction or data address and
      the access mode for the breakpoint is defined in a control
      register. This is the case of x86 and Super H.
      
      This patch adds a new CONFIG_HAVE_MIXED_BREAKPOINTS_REGS config
      that archs can select if they belong to the second case. Those
      will have their slot allocation merged for instructions and
      data breakpoints.
      
      The others will have a separate slot tracking between data and
      instruction breakpoints.
      Signed-off-by: default avatarFrederic Weisbecker <fweisbec@gmail.com>
      Acked-by: default avatarPaul Mundt <lethal@linux-sh.org>
      Cc: Will Deacon <will.deacon@arm.com>
      Cc: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
      Cc: K. Prasad <prasad@linux.vnet.ibm.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Paul Mackerras <paulus@samba.org>
      Cc: Ingo Molnar <mingo@elte.hu>
      0102752e
  20. 29 Apr, 2010 1 commit
  21. 27 Apr, 2010 1 commit
  22. 26 Apr, 2010 1 commit
  23. 13 Apr, 2010 1 commit
    • Paul Mundt's avatar
      sh: intc: userimask support. · 43b8774d
      Paul Mundt authored
      This adds support for hardware-assisted userspace irq masking for
      special priority levels. Due to the SR.IMASK interactivity, only some
      platforms implement this in hardware (including but not limited to
      SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU
      needs to wire this up on its own, for now only SH7786 is wired up as an
      example.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      43b8774d
  24. 12 Mar, 2010 1 commit
  25. 02 Feb, 2010 5 commits
  26. 29 Jan, 2010 1 commit
  27. 19 Jan, 2010 2 commits
    • Paul Mundt's avatar
      sh: SH7786 clock framework rewrite. · 43a1839c
      Paul Mundt authored
      This rewrites the SH7786 clock framework support completely. It's
      reworked to provide all of the DIV4 and MSTP function clocks. This brings
      it in line with the current clock framework code and lets us drop SH7786
      from the list of CPUs that require legacy CPG handling.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      43a1839c
    • Paul Mundt's avatar
      sh: Limit ioremap_prot() to 32bit pgprot parts. · 6d63e73d
      Paul Mundt authored
      Presently ioremap_prot() uses an unsigned long to pass the pgprot value
      around. This results in the upper half of the pgprot being chomped when
      using 64-bit pgprots on a 32-bit ABI (X2TLB and SH-5).
      
      As the only users of ioremap_prot() are presently legacy parts, this
      doesn't cause too much of an issue. In the future when the interface is
      converted to use pgprot_t directly this can be re-enabled for the other
      parts, too.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      6d63e73d
  28. 13 Jan, 2010 1 commit
  29. 12 Jan, 2010 1 commit
    • Paul Mundt's avatar
      sh: default to sparseirq. · ee2760ea
      Paul Mundt authored
      As SH has a very sparse IRQ map by default, all new CPUs and boards
      benefit from using sparseirq by default. Despite this, there are still a
      few stragglers (mostly due to using a fixed IRQ range for their FPGA
      IRQ mappings), and these still need to be converted over one by one. As
      these are now in the minority, and we do not want to encourage this sort
      of brain-damage in newer board ports, we force sparseirq on.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      ee2760ea
  30. 06 Jan, 2010 1 commit
  31. 29 Dec, 2009 1 commit
    • Paul Mundt's avatar
      sh: Only provide a PCLK definition for legacy CPG CPUs. · 8152a74b
      Paul Mundt authored
      As CPUs are migrated over to more fully-featured clock frameworks of
      their own and off of the legacy CPG code, they no longer have any real
      need for defining the PCLK value. The PCLK define in itself is already
      fairly misleading, as many boards get their input clocks from different
      sources, making this value fairly arbitrary anyways.
      
      Outside of the legacy CPG clock framework, the only place where this
      value is used is for deriving CLOCK_TICK_RATE, which we set back to the
      legacy PIT value that it was before the PCLK definitions were added in
      the first place.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      8152a74b
  32. 21 Dec, 2009 1 commit
  33. 08 Dec, 2009 1 commit
    • Paul Mundt's avatar
      sh: hw-breakpoints: Add preliminary support for SH-4A UBC. · 09a07294
      Paul Mundt authored
      This adds preliminary support for the SH-4A UBC to the hw-breakpoints API.
      Presently only a single channel is implemented, and the ptrace interface
      still needs to be converted. This is the first step to cleaning up the
      long-standing UBC mess, making the UBC more generally accessible, and
      finally making it SMP safe.
      
      An additional abstraction will be layered on top of this as with the perf
      events code to permit the various CPU families to wire up support for
      their own specific UBCs, as many variations exist.
      Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
      09a07294
  34. 27 Oct, 2009 2 commits