1. 14 May, 2014 2 commits
  2. 13 May, 2014 16 commits
  3. 12 May, 2014 16 commits
  4. 07 May, 2014 6 commits
    • Chris Wilson's avatar
      drm/i915: Flush request queue when waiting for ring space · 1cf0ba14
      Chris Wilson authored
      During the review of
      
      commit 1f70999f
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Mon Jan 27 22:43:07 2014 +0000
      
          drm/i915: Prevent recursion by retiring requests when the ring is full
      
      Ville raised the point that our interaction with request->tail was
      likely to foul up other uses elsewhere (such as hang check comparing
      ACTHD against requests).
      
      However, we also need to restore the implicit retire requests that certain
      test cases depend upon (e.g. igt/gem_exec_lut_handle), this raises the
      spectre that the ppgtt will randomly call i915_gpu_idle() and recurse
      back into intel_ring_begin().
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78023Reviewed-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
      [danvet: Remove now unused 'tail' variable as spotted by Brad.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      1cf0ba14
    • Chris Wilson's avatar
      drm/i915: Improve fallback ring waiting · dcfe0506
      Chris Wilson authored
      A few improvements to the fallback method for waiting upon ring space:
      
      1. Fix the start/end wait tracepoints to always be paired.
      2. Increase responsiveness of checking
      3. Mark the process as waiting upon io
      4. Check for signal interruptions
      Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: default avatarBrad Volkin <bradley.d.volkin@intel.com>
      [danvet: Drop the s/msleep/io_schedule_timeout/ change again since the
      latter isn't exported.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      dcfe0506
    • Ben Widawsky's avatar
      drm/i915: Make aliasing a 2nd class VM · 6e7186af
      Ben Widawsky authored
      There is a good debate to be had about how best to fit the aliasing
      PPGTT into the code. However, as it stands right now, getting aliasing
      PPGTT bindings is a hack, and done through implicit arguments. To make
      this absolutely clear, WARN and return an error if a driver writer tries
      to do something they shouldn't.
      
      I have no issue with an eventual revert of this patch. It makes sense
      for what we have today.
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      6e7186af
    • Ben Widawsky's avatar
      drm/i915: Use topdown allocation for PPGTT PDEs on gen6/7 · 3e8b5ae9
      Ben Widawsky authored
      It was always the intention to do the topdown allocation for context
      objects (Chris' idea originally). Unfortunately, I never managed to land
      the patch, but someone else did, so now we can use it.
      
      As a reminder, hardware contexts never need to be in the precious GTT
      aperture space - which is what is what happens with the normal bottom up
      allocation we do today. Doing a top down allocation increases the odds
      that the HW contexts can get out of the way, especially with per FD
      contexts as is done in full PPGTT
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3e8b5ae9
    • Imre Deak's avatar
      drm/i915: vlv: enable runtime PM · fd7f8cce
      Imre Deak authored
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      fd7f8cce
    • Imre Deak's avatar
      drm/i915: vlv: add runtime PM support · ddeea5b0
      Imre Deak authored
      Add runtime PM support for VLV, but leave it disabled. The next patch
      enables it.
      
      The suspend/resume sequence used is based on [1] and [2]. In practice we
      depend on the GT RC6 mechanism to save the HW context depending on the
      render and media power wells. By the time we run the runtime suspend
      callback the display side is also off and the HW context for that is
      managed by the display power domain framework.
      
      Besides the above there are Gunit registers that depend on a system-wide
      power well. This power well goes off once the device enters any of the
      S0i[R123] states. To handle this scenario, save/restore these Gunit
      registers. Note that this is not the complete register set dictated by
      [2], to remove some overhead, registers that are known not to be used are
      ignored. Also some registers are fully setup by initialization functions
      called during resume, these are not saved either. The list of registers
      can be further reduced, see the TODO note in the code.
      
      [1] VLV_gfx_clocking_PM_reset_y12w21d3 / "Driver D3 entry/exit"
      [2] VLV2_S0IXRegs
      
      v2:
      - unchanged
      v3:
      - fix s/GEN6_PMIIR/GEN6_PMIMR/ typo when saving/restoring registers
        (Ville)
      v4:
      - rebased on the previous patch fixing GEN register prefixes
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      [ rebased (according to v4) ]
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      ddeea5b0