- 21 Apr, 2023 21 commits
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Po-Ting Chen authored
Base on PSRSU specification, every seletive update frame need to use two SDP to indicate the frame active range. So we occupy another GSP1 for PSRSU execution. Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Po-Ting Chen <robin.chen@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Igor Kravchenko authored
Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Reviewed-by:
Igor Kravchenko <Igor.Kravchenko@amd.com> Tested-by:
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Meenakshikumar Somasundaram authored
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by:
Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Tested-by:
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Krunoslav Kovac authored
Enable 3-planes MPO for DCN321 by reporting max_slave_planes in DC caps for each ASIC. Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Tested-by:
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Aurabindo Pillai authored
DCN30 is missing a check for the pixel format 444 when using 16bits before setting the flag that Viewport exceeds the surface. Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by:
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Sherry Wang authored
[Why] DML calculation is different from HW formula. [How] Correct the bug to keep it same as HW formula. Reviewed-by:
Sherry Wang <Yao.Wang1@amd.com> Tested-by:
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Dmytro Laktyushkin authored
Dst_y can become negative in extreme odm 4to1 cases. While not strictly invalid, this should be limited to 0 for rq/dlg/ttu calculation. Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Tested-by:
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Jasdeep Dhillon authored
[Why] DCN32 resource contains code that uses FPU. [How] Moved code into DCN32 FPU Reviewed-by:
Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by:
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Aurabindo Pillai authored
For pstate change, allow DML to loop through all possible prefetch combinations so as to support more display configurations. Set the max and min prefetch modes to enable the sequence. Reviewed-by:
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Aurabindo Pillai authored
Set DRAM clock change state if retraining is required. Reviewed-by:
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Dillon Varone authored
[WHY&HOW] Low bpc timings are failing validation, port a patch to allow them to pass. Signed-off-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Srinivasan Shanmugam authored
Fix following checkpatch errors in amdgpu_discovery.c ERROR: space required after that ',' (ctx:VxV) ERROR: space required before the open parenthesis '(' ERROR: code indent should use tabs where possible Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Aurabindo Pillai authored
[Why&how] Update bounding box values as per hardware spec Fixes: 197485c6 ("drm/amd/display: Create dcn321_fpu file") Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Aurabindo Pillai authored
[Why & How] There's no need to clear GPINT register for DMUB when releasing it from reset. Fix that. Fixes: ac2e555e ("drm/amd/display: Add DMCUB source files and changes for DCN32/321") Reviewed-by:
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Srinivasan Shanmugam authored
Fix the below compiler error: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:229:11: error: unused variable 'otg_inst' [-Werror,-Wunused-variable] uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_hwseq.c:226:20: error: unused variable 'cmd' [-Werror,-Wunused-variable] union dmub_rb_cmd cmd; Cc: Aurabindo Pillai <aurabindo.pillai@amd.com> Cc: Jerry Zuo <jerry.zuo@amd.com> Cc: Yongqiang Sun <yongqiang.sun@amd.com> Signed-off-by:
Yongqiang Sun <Yongqiang.Sun@amd.com> Signed-off-by:
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Le Ma authored
Allocate different doorbell index for kiq/kcq rings on each die Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fix following checkpatch style errors in amdgpu_drv.c & amdgpu_device.c ERROR: exactly one space required after that #ifdef ERROR: spaces required around that '+=' (ctx:WxV) ERROR: space required before the open brace '{' ERROR: spaces required around that '||' (ctx:VxE) ERROR: space prohibited before that close parenthesis ')' ERROR: space required before the open parenthesis '(' ERROR: space required before the open brace '{' ERROR: code indent should use tabs where possible Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:Christian König <christian.koenig@amd.com> Signed-off-by:
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Srinivasan Shanmugam authored
Fix the following errors reported by checkpatch: ERROR: space prohibited before open square bracket '[' +#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type ERROR: code indent should use tabs where possible + query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLCV;$ Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by:
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Candice Li authored
Some ASICs support fatal error event but do not support pcie_bif ras. Signed-off-by:
Candice Li <candice.li@amd.com> Reviewed-by:
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Longlong Yao authored
The following call trace is observed when removing the amdgpu driver, which is caused by that BOs allocated for psp are not freed until removing. [61811.450562] RIP: 0010:amddrm_buddy_fini.cold+0x29/0x47 [amddrm_buddy] [61811.450577] Call Trace: [61811.450577] <TASK> [61811.450579] amdgpu_vram_mgr_fini+0x135/0x1c0 [amdgpu] [61811.450728] amdgpu_ttm_fini+0x207/0x290 [amdgpu] [61811.450870] amdgpu_bo_fini+0x27/0xa0 [amdgpu] [61811.451012] gmc_v9_0_sw_fini+0x4a/0x60 [amdgpu] [61811.451166] amdgpu_device_fini_sw+0x117/0x520 [amdgpu] [61811.451306] amdgpu_driver_release_kms+0x16/0x30 [amdgpu] [61811.451447] devm_drm_dev_init_release+0x4d/0x80 [drm] [61811.451466] devm_action_release+0x15/0x20 [61811.451469] release_nodes+0x40/0xb0 [61811.451471] devres_release_all+0x9b/0xd0 [61811.451473] __device_release_driver+0x1bb/0x2a0 [61811.451476] driver_detach+0xf3/0x140 [61811.451479] bus_remove_driver+0x6c/0xf0 [61811.451481] driver_unregister+0x31/0x60 [61811.451483] pci_unregister_driver+0x40/0x90 [61811.451486] amdgpu_exit+0x15/0x447 [amdgpu] For smu v13_0_2, if the GPU supports xgmi, refer to commit f5c7e779 ("drm/amdgpu: Adjust removal control flow for smu v13_0_2"), it will run gpu recover in AMDGPU_RESET_FOR_DEVICE_REMOVE mode when removing, which makes all devices in hive list have hw reset but no resume except the basic ip blocks, then other ip blocks will not call .hw_fini according to ip_block.status.hw. Since psp_free_shared_bufs just includes some software operations, so move it to psp_sw_fini. Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Longlong Yao <Longlong.Yao@amd.com> Signed-off-by:
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Cruise Hung authored
[Why & How] We missed resetting OUTBOX0 mailbox r/w pointer on DMUB reset. Fix it. Fixes: 6ecf9773 ("drm/amd/display: Fix DMUB outbox trace in S4 (#4465)") Signed-off-by:
Cruise Hung <Cruise.Hung@amd.com> Acked-by:
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- 20 Apr, 2023 4 commits
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Le Ma authored
Assign value here as the num_xcd is referenced in some gfx9 common path. Signed-off-by:
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Le Ma authored
Skip KCQ setup on slave xcc as there's no use case. Signed-off-by:
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Samson Tam authored
[Why] Workaround for DMCUB front door load [How] Clear GPINT after reset so its consistent Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Acked-by:
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Aurabindo Pillai authored
[Why&How] Fix CLK MGR early initialization and add logging. Fixes: 265280b9 ("drm/amd/display: add CLKMGR changes for DCN32/321") Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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- 18 Apr, 2023 15 commits
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Le Ma authored
v1: To support multple XCD case (Le) v2: unify naming style (Le) v3: apply the changes to gc v11_0 (Hawking) v4: apply the changes to gc SOC21 (Morris) Signed-off-by:
Morris Zhang <Shiwu.Zhang@amd.com> Signed-off-by:
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Le Ma authored
v1: To support multiple XCD case (Le) v2: introduce xcc index to gfx_v11_0_select_sh_se (Hawking) Signed-off-by:
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Le Ma authored
Change those v9_4_3 interfaces which are exposed in gfx_v9_0.c. For some active single-xcc emu models, the code path in gfx_v9_0.c is better to keep reserved for a while. Signed-off-by:
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Le Ma authored
Each XCD needs to be initialized respectively. The major changes are: 1. add iteration to do rlc/kiq/kcq init/fini for each xcd 2. load rlc/mec microcode to each xcd 3. add argument to specify xcc index in initialization functions Signed-off-by:
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Le Ma authored
To support grbm select for multiple XCD case. v2: unify naming style Signed-off-by:
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Le Ma authored
To prepare for gc v9_4_3 specific feature. v2: fix exports (Alex) Signed-off-by:
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Le Ma authored
v1: Modify kiq_init/fini, mqd_sw_init/fini and enable/disable_kcq to adapt to multi-die case. Pass 0 as default to all asics with single xcc (Le) v2: squash commits to avoid breaking the build (Le) v3: unify naming style (Le) v4: apply the changes to gc v11_0 (Hawking) Signed-off-by:
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Le Ma authored
This will benifit the mqd indexing for kiq/kcq in multi XCD case. Signed-off-by:
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Le Ma authored
To allocate independent queue_bitmap for each XCD, then the old bitmap policy can be continued to use with a clear logic. Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs. v2: squash commits to avoid breaking the build v3: unify naming style Signed-off-by:
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Le Ma authored
v1: more kiq instances are a available in SOC (Le) v2: squash commits to avoid breaking the build (Le) v3: make the conversion for gfx/mec v11_0 (Hawking) Signed-off-by:
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Nikita Zhandarovich authored
Several calls to ci_dpm_fini() will attempt to free resources that either have been freed before or haven't been allocated yet. This may lead to undefined or dangerous behaviour. For instance, if r600_parse_extended_power_table() fails, it might call r600_free_extended_power_table() as will ci_dpm_fini() later during error handling. Fix this by only freeing pointers to objects previously allocated. Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Fixes: cc8dbbb4 ("drm/radeon: add dpm support for CI dGPUs (v2)") Co-developed-by:
Natalia Petrova <n.petrova@fintech.ru> Signed-off-by:
Nikita Zhandarovich <n.zhandarovich@fintech.ru> Signed-off-by:
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Tom Rix authored
cpp_check reports drivers/gpu/drm/amd/display/modules/freesync/freesync.c:1143:17: style: Variable 'oldest_index' is assigned a value that is never used. [unreadVariable] oldest_index = 0; ^ This variable is not used so remove. Signed-off-by:Tom Rix <trix@redhat.com> Signed-off-by:
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Alan Liu authored
[Why] After gpu-reset, sometimes the driver fails to enable vblank irq, causing flip_done timed out and the desktop freezed. During gpu-reset, we disable and enable vblank irq in dm_suspend() and dm_resume(). Later on in amdgpu_irq_gpu_reset_resume_helper(), we check irqs' refcount and decide to enable or disable the irqs again. However, we have 2 sets of API for controling vblank irq, one is dm_vblank_get/put() and another is amdgpu_irq_get/put(). Each API has its own refcount and flag to store the state of vblank irq, and they are not synchronized. In drm we use the first API to control vblank irq but in amdgpu_irq_gpu_reset_resume_helper() we use the second set of API. The failure happens when vblank irq was enabled by dm_vblank_get() before gpu-reset, we have vblank->enabled true. However, during gpu-reset, in amdgpu_irq_gpu_reset_resume_helper() vblank irq's state checked from amdgpu_irq_update() is DISABLED. So finally it disables vblank irq again. After gpu-reset, if there is a cursor plane commit, the driver will try to enable vblank irq by calling drm_vblank_enable(), but the vblank->enabled is still true, so it fails to turn on vblank irq and causes flip_done can't be completed in vblank irq handler and desktop become freezed. [How] Combining the 2 vblank control APIs by letting drm's API finally calls amdgpu_irq's API, so the irq's refcount and state of both APIs can be synchronized. Also add a check to prevent refcount from being less then 0 in amdgpu_irq_put(). v2: - Add warning in amdgpu_irq_enable() if the irq is already disabled. - Call dc_interrupt_set() in dm_set_vblank() to avoid refcount change if it is in gpu-reset. v3: - Improve commit message and code comments. Signed-off-by:
Alan Liu <HaoPing.Liu@amd.com> Reviewed-by:
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Colin Ian King authored
There is a spelling mistake in the smu_i2c_bus_access prototype. Fix it. Signed-off-by:
Colin Ian King <colin.i.king@gmail.com> Signed-off-by:
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Bas Nieuwenhuizen authored
This info would be used by radv to figure out when we need to split a submission into multiple submissions. radv currently has a limit of 192 which seems to work for most gfx submissions, but is way too high for e.g. compute or sdma. Userspace is available at https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3 v3: Completely rewrote based on suggestion of making it a separate query. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2498Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Signed-off-by:
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