- 02 Jun, 2015 1 commit
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Hongzhou Yang authored
Add ies/smt support for MSDC3. Also fix ies bug for pin 106 and 107. Signed-off-by:
Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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- 01 Jun, 2015 7 commits
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Geert Uytterhoeven authored
Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by:
Simon Horman <horms+renesas@verge.net.au> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Masahiro Yamada authored
Only this member, pins, is defined as "struct ... const *", but the others in this struct, pinlops, pmxops, confops, etc. are defined as "const struct ... *". Swap the "struct pinctrl_pin_desc" and "const" for consistency. Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
This "const" claims the get_function_groups callback never changes the given num_groups pointer. It is always true in C language, so not worth mentioning. Signed-off-by:
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Masahiro Yamada authored
The address for SD0_WP_CD_SEL, SD1_WP_CD_SEL is 0xf8000830, 0xf8000834, respectively. Each offset address must be prefixed with 0x. Fixes: add958ce "pinctrl: Add driver for Zynq" Signed-off-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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Masahiro Yamada authored
The offset to the mux register is missing. Fixes: add958ce "pinctrl: Add driver for Zynq" Signed-off-by:
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Jon Hunter authored
Commit e5b3b2d9 ("pinctrl: allows not to define the get_group_pins operation") allows pin controllers not to register the get_group_pins() function. However, a side-effect of not registering this function is that pins are not allocated and potentially multiple devices could attempt to configure the same pins [1]. Although this problem exists in the pinctrl core, because only a few devices are impacted by this, fix this for tegra-xusb by adding the get_group_pins() function. Please note that in addition to adding the get_group_pins() functions the pins/lanes for the tegra-xusb also need to be registered when calling pinctrl_register(). This also allows the current pinmux state to be viewed by the debugfs node "pinmux-pins" for the tegra-xusb pad controller. [1] http://www.spinics.net/lists/linux-gpio/msg05810.htmlSigned-off-by:
Jon Hunter <jonathanh@nvidia.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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Jon Hunter authored
The structure tegra_xusb_padctl_group is defined but never used and so remove this. Signed-off-by:
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- 28 May, 2015 1 commit
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Linus Walleij authored
If we know we are using a strict pin controller (one that cannot mix device functions+group use and GPIO) we can be a bit more specific in debugfs, just print either device-function-group or GPIO consumer for the pin. Let's do that to be helpful. Cc: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
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- 20 May, 2015 1 commit
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Linus Walleij authored
X86_64 allmodconfig screams like so: warning: (PINCTRL_MT6397) selects PINCTRL_MTK_COMMON which has unmet direct dependencies (PINCTRL && (ARCH_MEDIATEK || COMPILE_TEST) && OF) So add OF to dependencies to shut up this warning. Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Signed-off-by:
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- 19 May, 2015 13 commits
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Yoshihiro Shimoda authored
Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by:
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Wei Chen authored
The Pinctrl module (ioc) controls the Pad's function select (each pad can have 8 functions), Pad's Drive Strength, Pad's Pull Select and Pad's Input Disable status. The ioc has two modules, ioc_top & ioc_rtc. Both of these two modules have function select/clear, Pull select and Drive Strength registers. But only ioc_rtc has input-disable registers. The Pads on ioc_top have to access ioc_rtc to set their input-disable status and intpu-disable-value. So have to use one ioc driver instance to drive these two ioc modules at the same time, and each ioc module will be treat as one bank on the "IOC Device". The GPIO Controller controls the GPIO status if the Pad has been config as GPIO by Pinctrl already. Includes the GPIO Input/output, Interrupt type, Interrupt Status, and Set/Get Values. The GPIO pull up/down are controlled by Pinctrl. There are 7 GPIO Groups and splited into 3 MACROs in atlas7. The GPIO Groups in one MACRO share one GPIO controllers, each GPIO Group are treated as one GPIO bank. For example: In VDIFM macro, there is one GPIO Controller, it has 3 banks to control 3 gpio groups. Its gpio name space is from 0 to 95. The Device Tree can be written as following: gpio-ranges = <&pinctrl 0 0 0>, <&pinctrl 32 0 0>, <&pinctrl 64 0 0>; gpio-ranges-group-names = "gnss_gpio_grp", "lcd_vip_gpio_grp", "sdio_i2s_gpio_grp"; bank#0 is from 0~31, the pins are from pinctrl's "gnss_gpio_grp". bank#2 is from 32~63, the pins are from pinctrl's "lcd_vip_gpio_grp". bank#3 is from 64~95, the pins are from pinctrl's "sdio_i2s_gpio_grp". Signed-off-by:
Wei Chen <Wei.Chen@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
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Masahiro Yamada authored
This function is only referenced in this file. Signed-off-by:
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Yoshihiro Shimoda authored
Signed-off-by:
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Yingjoe Chen authored
MT8127 pinctrl/eint are similar to mt8135 and mt8173, add support for mt8127 using mediatek common pinctrl driver. Signed-off-by:
Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by:
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Hongzhou Yang authored
Add mt6397 support using mediatek common pinctrl driver. mt6397 is a PMIC, and pinctrl/GPIO is part of 6397 chip. Pinctrl/GPIO driver should obtain regmap from PMIC, so adding this support to common code. Also, mt6397 is no need to support interrupt controller, so changing common code to skip it. Signed-off-by:
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Hongzhou Yang authored
Input enable and smt setting have different register, modify code to fix it. Several mediatek soc use similar input enable/smt setting procedure as mt8173, some soc use generic input enable/smt setting, some soc has no input enable/smt setting. Adding common code to handle all those cases, so future soc driver can use it. Signed-off-by:
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Yingjoe Chen authored
Several mediatek soc use similar pull setting procedure as mt8173, the pupd enable and resistance setting are in the same register. Add common code mtk_pctrl_spec_pull_set_samereg out of spec_pull_set in mt8173 to handle this case, so future soc driver can use it. Signed-off-by:
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Yingjoe Chen authored
struct mtk_desc_pin.chip, mtk_pinctrl_devdata.invser_offset and mtk_pinctrl_devdata.chip_type are never used in code. Remove them. Some per-pin data are using int for pin number and offsets. Change to short and rearrange to reduce const data size. Signed-off-by:
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Hongzhou Yang authored
Add pinfunc header file, mt8135/mt8173 relate dts will include it. Signed-off-by:
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Hongzhou Yang authored
Since 6397 is no need to support interrupt controller, moving interrupt controller relate property to optional list. Also adding mt8173 and mt8127 to bindings. Signed-off-by:
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Joachim Eastwood authored
Add the required group function map and fill it at probe using the pin capabilities information already present in the driver. Signed-off-by:
Joachim Eastwood <manabian@gmail.com> Signed-off-by:
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Ray Jui authored
Fixed a small typo in the Cygnus GPIO driver Signed-off-by:
Jason Uy <jasonuy@broadcom.com> Signed-off-by:
Ray Jui <rjui@broadcom.com> Signed-off-by:
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- 12 May, 2015 10 commits
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Andrew Bresticker authored
Add a driver for the pin controller present on the IMG Pistachio SoC. This driver provides pinmux and pinconfig operations as well as GPIO and IRQ chips for the GPIO banks. Changes from v4: - Switched to using gpiochip_add_pin_range(). - Fixed up Kconfig entry. Changes from v3: - Addressed review comments from Ezequiel. Changes from v2: - Removed module stuff which would be compiled out. Changes from v1: - Addressed review comments from Linus. - Changed compatible string to "img,pistachio-system-pinctrl". - Look for GPIO sub-nodes by name. - A couple of bug fixes. Signed-off-by:
Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by:
Govindraj Raja <govindraj.raja@imgtec.com> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@imgtec.com> Signed-off-by:
Kevin Cernekee <cernekee@chromium.org> Signed-off-by:
Andrew Bresticker <abrestic@chromium.org> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Joachim Eastwood authored
Both pconf_get_pin and pconf_set_pin needs to lookup pin cap based on the pin number. Create a common helper function that both functions can use that also handles the case where no pin number is found in the pins array. This also fixes a small bug in pconf_get_pin where pconf_get_i2c0 would use the pins array index rather than the pin number. Signed-off-by:
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Geert Uytterhoeven authored
As of commit 9d07d414 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic ARM multi-platform builds. Hence CONFIG_ARCH_MULTIPLATFORM is always set, and the check can be removed. Signed-off-by:
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Ulrich Hecht authored
Also renames "R-Car M2" to "R-Car M2-W" to avoid confusion. Signed-off-by:
Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by:
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Ulrich Hecht authored
Signed-off-by:
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Ulrich Hecht authored
Regarding pin control, r8a7791 and r8a7793 are identical, so it is sufficient to add an sh_pfc_soc_info structure to enable r8a7793 support. Signed-off-by:
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Geert Uytterhoeven authored
The last serial port is called "SCIFB", not "SCIFAB". Signed-off-by:
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Mika Westerberg authored
Intel Sunrisepoint-H is a desktop version of the PCH (Platform Controller Hub). It has slightly different pin configuration compared to the LP version. This patch adds support for Sunrisepoint-H to the existing pinctrl-sunrisepoint.c driver. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Geert Uytterhoeven authored
Signed-off-by:
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Geert Uytterhoeven authored
As of commit 9d07d414 ("ARM: shmobile: r8a73a4: ape6evm: Remove legacy platform"), r8a73a4 is only supported in generic DT-only ARM multi-platform builds. The driver doesn't need to match platform devices by name anymore, hence remove the corresponding platform_device_id entry. Signed-off-by:
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- 06 May, 2015 7 commits
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Fabian Frederick authored
Inspired by scripts/coccinelle/api/err_cast.cocci Signed-off-by:
Fabian Frederick <fabf@skynet.be> Signed-off-by:
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Krzysztof Kozlowski authored
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by:
Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by:
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Krzysztof Kozlowski authored
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by:
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Markus Pargmann authored
The old format to define pinctrl settings for imx in DT has two hierarchy levels. The first level are function device nodes. The second level are pingroups which contain a property fsl,pins. The original intention was to define all pin functions in a single dtsi file and just reference the correct ones in the board files. This idea was rejected some time ago leading to the current design to have all the pinfunctions defined in the board files. So we don't need the function device nodes anymore. This patch changes the pinctrl driver to accept devicetrees which do not have the first hierarchy level, function device nodes. For example karo-tx25 already has such a devicetree. Old devicetrees are still parsed and supported. Signed-off-by:
Markus Pargmann <mpa@pengutronix.de> Acked-by:
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Signed-off-by:
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Helmut Buchsbaum authored
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI interfaces, SS0, SS1 and SS2 have to be configured separately as they may be used as simple GPIO lines. This, of course, has to be considered in the devicetree, so pin controller configuration for e.g. an SPI0 using SS0 and SS1 only might look like the following snippet (derived from the example of chapter "17.5.3 MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used as GPIO instead of being occupied by SPI0 SS2 function. Note the separate pinmux function for the slave select signals: pinctrl_spi0_default: spi0-default { mux_spi { function = "spi0"; groups = "spi0_0_grp"; }; mux_ss { function = "spi0_ss"; groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp"; } conf-output { pins = "MIO16", "MIO21"; slew-rate = <0>; bias-disable; low-power-disable; io-standard = <1>; }; conf-input { pins = "MIO17"; slew-rate = <0>; bias-high-impedance; low-power-disable; io-standard = <1>; }; conf-select { pins = "MIO18", "MIO19"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; pinctrl_gpio0_default { mux { function = "gpio0"; groups = "gpio0_20_grp" }; conf { pins = "MIO20"; slew-rate = <0>; bias-pull-up; low-power-disable; io-standard = <1>; }; }; Signed-off-by:Helmut Buchsbaum <helmut.buchsbaum@gmail.com> Acked-by:
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Linus Walleij authored
Assign GPIO chip and irqchip to the GPIO container dynamically, so we can set a unique name for each GPIO irqchip and see what chip the hwirq offset actually relates to. Signed-off-by: -
Linus Walleij authored
This activates strict mode muxing for the Nomadik pin controllers, as these do not allow GPIO and functions to use the same pin simultaneously. Signed-off-by:
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