- 21 Oct, 2016 10 commits
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Jiri Olsa authored
Using resort callbacks to compute the columns' width. Computing only the global ones, c2c entries have fixed width only. Signed-off-by:
Jiri Olsa <jolsa@kernel.org> Cc: Andi Kleen <andi@firstfloor.org> Cc: David Ahern <dsahern@gmail.com> Cc: Don Zickus <dzickus@redhat.com> Cc: Joe Mario <jmario@redhat.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/n/tip-zyayvq2u3dzyf3y7i9jza0lw@git.kernel.orgSigned-off-by:
Arnaldo Carvalho de Melo <acme@redhat.com>
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Jiri Olsa authored
Allowing user to configure the way the single cacheline data are sorted after being sorted by offset. Adding 'c' option to specify sorting fields for single cacheline: -c, --coalesce <coalesce fields> coalesce fields: pid,tid,iaddr,dso It's allowed to use following combination of fields: pid - process pid tid - process tid iaddr - code address dso - shared object Tested-by: -
Jiri Olsa authored
Currently we sort and limit displayed data based on the remote HITMs count. Adding support to switch to local HITMs via --display option: --display ... lcl,rmt Signed-off-by: -
Jiri Olsa authored
Add a limit for entries number of the cachelines table entries. By default now it's the 0.0005% minimum of remote HITMs. Also display only cachelines with remote hitm or store data. Signed-off-by:
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Jiri Olsa authored
Add --call-graph option to properly setup callchain code. Adding default settings to display callchains whenever they are stored in the perf.data. Committer Notes: Testing it: [root@jouet ~]# perf c2c record -a -g sleep 5 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 5.331 MB perf.data (4263 samples) ] [root@jouet ~]# perf evlist -v cpu/mem-loads,ldlat=30/P: type: 4, size: 112, config: 0x1cd, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|CALLCHAIN|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3, mmap_data: 1, sample_id_all: 1, mmap2: 1, comm_exec: 1, { bp_addr, config1 }: 0x1f cpu/mem-stores/P: type: 4, size: 112, config: 0x82d0, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|CALLCHAIN|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, freq: 1, precise_ip: 3, sample_id_all: 1 [root@jouet ~]# perf c2c report --stats ================================================= Trace Event Information ================================================= Total records : 4263 Locked Load/Store Operations : 220 Load Operations : 2130 Loads - uncacheable : 1 Loads - IO : 7 Loads - Miss : 86 Loads - no mapping : 5 Load Fill Buffer Hit : 609 Load L1D hit : 612 ================================================= Trace Event Information ================================================= Total records : 4263 Locked Load/Store Operations : 220 Load Operations : 2130 Loads - uncacheable : 1 Loads - IO : 7 Loads - Miss : 86 Loads - no mapping : 5 Load Fill Buffer Hit : 609 Load L1D hit : 612 Load L2D hit : 27 Load LLC hit : 607 Load Local HITM : 15 Load Remote HITM : 0 Load Remote HIT : 0 Load Local DRAM : 176 Load Remote DRAM : 0 Load MESI State Exclusive : 176 Load MESI State Shared : 0 Load LLC Misses : 176 LLC Misses to Local DRAM : 100.0% LLC Misses to Remote DRAM : 0.0% LLC Misses to Remote cache (HIT) : 0.0% LLC Misses to Remote cache (HITM) : 0.0% Store Operations : 2133 Store - uncacheable : 0 Store - no mapping : 1 Store L1D Hit : 1967 Store L1D Miss : 165 No Page Map Rejects : 145 Unable to parse data source : 0 ================================================= Global Shared Cache Line Event Information ================================================= Total Shared Cache Lines : 15 Load HITs on shared lines : 26 Fill Buffer Hits on shared lines : 7 L1D hits on shared lines : 3 L2D hits on shared lines : 0 LLC hits on shared lines : 16 Locked Access on shared lines : 2 Store HITs on shared lines : 8 Store L1D hits on shared lines : 7 Total Merged records : 23 ================================================= c2c details ================================================= Events : cpu/mem-loads,ldlat=30/P : cpu/mem-stores/P [root@jouet ~]# [root@jouet ~]# perf c2c report Shared Data Cache Line Table (2378 entries) Total --- LLC Load Hitm -- -- Store Reference - - Load Dram - LLC Total - Core Load Hit - Cacheline records %hitm Total Lcl Rmt Total L1Hit L1Miss Lcl Rmt Ld Miss Loads FB L1 L2 - 0xffff880024380c00 10 0.00% 0 0 0 6 6 0 0 0 0 4 1 3 0 - 0.13% _raw_spin_lock_irqsave - 0.07% ep_poll sys_epoll_wait do_syscall_64 return_from_SYSCALL_64 + 0x103573 - 0.05% ep_poll_callback __wake_up_common - __wake_up_sync_key - 0.02% pipe_read __vfs_read vfs_read sys_read do_syscall_64 return_from_SYSCALL_64 0xfdad + 0.02% sock_def_readable + 0.02% ep_scan_ready_list.constprop.12 + 0.00% mutex_lock + 0.00% __wake_up_common + 0xffff880024380c40 1 0.00% 0 0 0 1 1 0 0 0 0 0 0 0 0 + 0xffff880024380c80 1 0.00% 0 0 0 0 0 0 0 0 0 1 0 0 0 - 0xffff8800243e9f00 1 0.00% 0 0 0 1 1 0 0 0 0 0 0 0 0 enqueue_entity enqueue_task_fair activate_task ttwu_do_activate try_to_wake_up wake_up_process hrtimer_wakeup __hrtimer_run_queues hrtimer_interrupt local_apic_timer_interrupt smp_apic_timer_interrupt apic_timer_interrupt cpuidle_enter call_cpuidle help ------------- And when presing 'd' to see the cacheline details: Cacheline 0xffff880024380c00 ----- HITM ----- -- Store Refs -- --------- cycles ----- cpu Rmt Lcl L1 Hit L1 Miss Off Pid Tid rmt hitm lcl hitm load cnt Symbol - 0.00% 0.00% 100.00% 0.00% 0x0 1473 1474:Chrome_ChildIOT 0 0 41 2 [k] _raw_spin_lock_irqsave [kernel] - _raw_spin_lock_irqsave - 51.52% ep_poll sys_epoll_wait do_syscall_64 return_from_SYSCALL_64 - 0x103573 47.19% 0 4.33% 0xc30bd - 35.93% ep_poll_callback __wake_up_common - __wake_up_sync_key - 18.20% pipe_read __vfs_read vfs_read sys_read do_syscall_64 return_from_SYSCALL_64 0xfdad - 17.73% sock_def_readable unix_stream_sendmsg sock_sendmsg ___sys_sendmsg __sys_sendmsg sys_sendmsg do_syscall_64 return_from_SYSCALL_64 __GI___libc_sendmsg 0x12c036af1fc0 0x16a4050 0x894928ec83485354 + 12.45% ep_scan_ready_list.constprop.12 + 0.00% 0.00% 0.00% 0.00% 0x8 1473 1474:Chrome_ChildIOT 0 0 102 1 [k] mutex_lock [kernel] + 0.00% 0.00% 0.00% 0.00% 0x38 1473 1473:chrome 0 0 88 1 [k] __wake_up_common [kernel] help Signed-off-by: -
Jiri Olsa authored
Display c2c related configuration options/setup. So far it's output of monitored events: $ perf c2c report --stats ... ================================================= c2c details ================================================= Events : cpu/mem-loads,ldlat=50/pp : cpu/mem-stores/pp Signed-off-by: -
Jiri Olsa authored
Display global shared cachelines related stats table as part of the stdio output or when --stats option is speicified: $ perf c2c report --stats ... ================================================= Global Shared Cache Line Event Information ================================================= Total Shared Cache Lines : 1384 Load HITs on shared lines : 5995 Fill Buffer Hits on shared lines : 1726 L1D hits on shared lines : 1943 L2D hits on shared lines : 0 LLC hits on shared lines : 1360 Locked Access on shared lines : 1993 Store HITs on shared lines : 1504 Store L1D hits on shared lines : 1446 Total Merged records : 3527 Original-patch-by:Dick Fowles <rfowles@redhat.com> Original-patch-by:
Don Zickus <dzickus@redhat.com> Signed-off-by:
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Jiri Olsa authored
Display global stats table as part of the stdio output or when --stats option is speicified: $ perf c2c report --stats ================================================= Trace Event Information ================================================= Total records : 41237 Locked Load/Store Operations : 4075 Load Operations : 20526 Loads - uncacheable : 0 Loads - IO : 0 Loads - Miss : 552 Loads - no mapping : 31 Load Fill Buffer Hit : 7333 Load L1D hit : 6398 Load L2D hit : 144 Load LLC hit : 4889 Load Local HITM : 1185 Load Remote HITM : 838 Load Remote HIT : 52 Load Local DRAM : 183 Load Remote DRAM : 106 Load MESI State Exclusive : 289 Load MESI State Shared : 0 Load LLC Misses : 1179 LLC Misses to Local DRAM : 15.5% LLC Misses to Remote DRAM : 9.0% LLC Misses to Remote cache (HIT) : 4.4% LLC Misses to Remote cache (HITM) : 71.1% Store Operations : 20711 Store - uncacheable : 0 Store - no mapping : 1 Store L1D Hit : 20158 Store L1D Miss : 552 No Page Map Rejects : 7 Unable to parse data source : 0 Original-patch-by: -
Jiri Olsa authored
Adding simple TUI cacheline browser. It triggers when you press 'd' in the main browser on the specific cacheline. It allows to navigate through cacheline's offsets and display callchains (implemented in following patches). Signed-off-by:
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Jiri Olsa authored
Add the main cachelines TUI browser. It allows to navigate through cachelines and display their details and callchains (implemented in the following patches). Signed-off-by:
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- 19 Oct, 2016 30 commits
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Jiri Olsa authored
Adding the --stdio option output support. The output tables are dumped directly to the stdio. $ perf c2c report ================================================= Shared Data Cache Line Table ================================================= # # Total ----- LLC Load Hitm ----- ---- Store Reference ---- --- Load Dram ---- LLC Total ----- Core Load Hit ----- -- LLC Load Hit -- # Cacheline records %hitm Total Lcl Rmt Total L1Hit L1Miss Lcl Rmt Ld Miss Loads FB L1 L2 Llc Rmt # .................. ....... ....... ....... ....... ....... ....... ....... ....... ........ ........ ....... ....... ....... ....... ....... ........ ........ # 0xffff88000235f840 17 0.00% 0 0 0 17 17 0 0 0 0 0 0 0 0 0 0 ... ================================================= Shared Cache Line Distribution Pareto ================================================= # # ----- HITM ----- -- Store Refs -- Data address ---------- cycles ---------- cpu Shared # Rmt Lcl L1 Hit L1 Miss Offset Pid Tid rmt hitm lcl hitm load cnt Symbol Object Node # ....... ....... ....... ....... .................. ....... ..................... ........ ........ ........ ........ .................... ................. .... # ------------------------------------------------------ 0 0 17 0 0xffff88000235f840 ------------------------------------------------------ 0.00% 0.00% 5.88% 0.00% 0x0 11474 11474:kworker/u16:5 0 0 0 1 [k] rmap_walk_file [kernel.kallsyms] 0 0.00% 0.00% 5.88% 0.00% 0x10 11474 11474:kworker/u16:5 0 0 0 1 [k] lock_page_memcg [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x20 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapping [kernel.kallsyms] 0 0.00% 0.00% 64.71% 0.00% 0x28 11474 11474:kworker/u16:5 0 0 0 1 [k] __test_set_page_writeback [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x30 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapped [kernel.kallsyms] 0 ... Signed-off-by: -
Jiri Olsa authored
Set resort/display fields for both cachelines and single cacheline displays. Cachelines are sorted on: rmt_hitm will be made configurable in following patches. Following fields are display for cachelines: dcacheline tot_recs percent_hitm tot_hitm,lcl_hitm,rmt_hitm stores,stores_l1hit,stores_l1miss dram_lcl,dram_rmt ld_llcmiss tot_loads ld_fbhit,ld_l1hit,ld_l2hit ld_lclhit,ld_rmthit The single cacheline is sort by: offset,rmt_hitm,lcl_hitm will be made configurable in following patches. Following fields are display for each cacheline: percent_rmt_hitm percent_lcl_hitm percent_stores_l1hit percent_stores_l1miss offset pid tid mean_rmt mean_lcl mean_load cpucnt symbol dso node Signed-off-by:
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Jiri Olsa authored
Allow to setup number of header lines for c2c hists objects. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: cl_srcline It displays source line related to the code address that accessed cacheline. It's a wrapper to global srcline sort entry. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: cpucnt It displays number of distinct cpus that hit cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: median, mean_rmt, mean_lcl, mean_load, stddev It displays statistics hits related to cacheline accesses. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: node It displays nodes hits related to cacheline accesses. The node filed comes in 3 flavors: - node IDs separated by ',' - node IDs with stats for each ID, in following format: Node{cpus %hitms %stores} - node IDs with list of affected CPUs in following format: Node{cpu list} User can switch the flavor with -N option (-NN,-NNN). It will be available in TUI to switch this with 'n' key. Signed-off-by: -
Jiri Olsa authored
They are to be displayed in the single cacheline output: symbol, dso They are wrappers for global sort_sym and sort_dso sort entries with c2c specific headers. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: tid It's a wrapper for global sort_thread sort entry with c2c specific header. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the single cacheline output: pid We currently don't have a single 'pid' sort/display entry, which would output just pid number, hence adding it into c2c code. Signed-off-by:
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Jiri Olsa authored
They are to be displayed in the main cachelines overall output: dram_lcl, dram_rmt They display DRAM rmt/lcl access numbers for specific cacheline. Signed-off-by:
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Jiri Olsa authored
They are to be displayed in the single cacheline output: percent_rmt_hitm, percent_lcl_hitm, percent_stores_l1hit, percent_stores_l1miss They display percentage of HITMs/stores for specific offset in the cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: percent_hitm It displays HITMs percentage for cacheline. It counts remote HITMs at the moment, but it is changed later to support local as well, based on the sort configuration. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: tot_loads It displays sum of all load accesses for cacheline. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: tot_recs It displays sum of all cachelines accesses. Signed-off-by:
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Jiri Olsa authored
It is to be displayed in the main cachelines overall output: ld_llcmiss It displays bare number of LLC misses for cacheline. Signed-off-by:
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Jiri Olsa authored
Add 2 LLC load related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_lclhit, ld_rmthit They display bare numbers of LLC and remote loads for cacheline. Signed-off-by:
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Jiri Olsa authored
Add 3 loads related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_fbhit, ld_l1hit, ld_l2hit They all display bare numbers of loads for FB (Fill Buffer), L1 and L2 cache. Signed-off-by:
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Jiri Olsa authored
Add 5 stores related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: stores, stores_l1hit, stores_l1miss The latter 2 are to be displayed within single cacheline output: cl_stores_l1hit, cl_stores_l1miss They all display bare numbers of stores for cacheline or its related offsets. Signed-off-by:
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Jiri Olsa authored
Adding 5 hitm related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: tot_hitm, lcl_hitm, rmt_hitm The latter 2 are to be displayed within single cacheline output: cl_rmt_hitm, cl_lcl_hitm They all display bare numbers of remote/local/total HITMs for cacheline or its related offsets. Signed-off-by:
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Jiri Olsa authored
It displays the code address (as hex number) responsible for the accesses. Using c2c wrapper to standard 'symbol_iaddr' object to define own header and simple (just address) code address output. Signed-off-by:
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Jiri Olsa authored
It displays cacheline offset as hex number. Signed-off-by:
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Jiri Olsa authored
It displays cacheline address as hex number. Using c2c wrapper to standard 'dcacheline' object to defined own header and simple (just address) cacheline output. Signed-off-by:
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Jiri Olsa authored
Adding helping macros to define header objects. It will be used in following patches, that add new dimensions. The c2c report will support 2 line headers, hence we only define line[0/1] in macros. Signed-off-by:
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Jiri Olsa authored
Decoding and storing c2c_stats for each hist entry. Changing related function to work with c2c_* objects. Signed-off-by:
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Jiri Olsa authored
Store cacheline related entries in nested hist object for each cacheline data. Nested entries are sorted by 'offset' within related cacheline. We will allow specific sort keys to be configured for nested cacheline data entries in following patches. Signed-off-by:
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Jiri Olsa authored
Adding basic sample processing specific hist_entry allocation callbacks (via hists__add_entry_ops). Overloading 'struct hist_entry' object with new 'struct c2c_hist_entry'. The new hist entry object will carry specific stats and nested hists objects. Signed-off-by:
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Jiri Olsa authored
Fallback to standard dimensions in case we don't find the dimension within c2c ones. Signed-off-by:
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Jiri Olsa authored
Allow to reuse 'struct sort_entry' objects within c2c dimension support. In case the 'struct sort_entry' object meets the need of c2c report we will use it directly in following patches. Signed-off-by:
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Jiri Olsa authored
Adding bare bones of dimension support for c2c report. Main interface functions are: c2c_hists__init c2c_hists__reinit which re/initialize 'struct c2c_hists' object with sort/display entries string, in a similar way that setup_sorting function does. We overload the dimension to provide multi line header support for sort/display entries. Also we overload base 'struct perf_hpp_fmt' object with 'struct c2c_fmt' to define c2c specific functions to deal with multi line headers and spans. Signed-off-by:
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