In the error path of fsi_master_register(), we currently
use device_unregister(). This will cause the last reference
to the structure to be dropped, thus freeing the enclosing
structure, which isn't what the callers want.

Use device_del() instead so that we return to the caller
with a refcount of 1. The caller can then assume that it
must use put_device() after a call to fsi_master_register()
regardless of whether the latter suceeded or failed.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Some definitions are generic to the FSI protocol or any
give master implementation. Rename them to remove the
"GPIO" prefix in preparation for moving them to a common
header.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

# Conflicts:
#	drivers/fsi/fsi-master-gpio.c

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

This adds a few more tracepoints that have proven useful when
debugging issues with the FSI bus.

This also makes echo_delay() use clock_zeros() instead of
open-code it in order to share the tracepoint.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

To configure the send and echo delays
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

What the driver called "FSI_GPIO_PRIME_SLAVE_CLOCKS" is what
the FSI spec calls tSendDelay and should be 16 clocks by
default.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

Those values control the amount of "dummy" clocks between commands and
between a command and its response.

This adds a way to configure them from sysfs (to be later extended to
defaults in the device-tree). The default remains 16 (the HW default).

This is only supported if the backend supports the new link_config()
callback to configure the generation of those delays.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
---

Move fsi_slave_set_smode() and its helpers to before it's
first user and remove the corresponding forward declaration.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>

"dev" is dereferences before it's checked.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

The driver calls of_platform_device_create() which is only available
if OF_ADDRESS is enabled. When building sparc64 images, this results
in

ERROR: "of_platform_device_create" [drivers/fsi/fsi-sbefifo.ko] undefined!

Fixes: 9f4a8a2d ("fsi/sbefifo: Add driver for the SBE FIFO")
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

There was no unlock of the FFDC mutex.

Fixes: 9f4a8a2d ("fsi/sbefifo: Add driver for the SBE FIFO")
Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

This was too hard to split ... this adds a number of features
to the SCOM user interface:

 - Support for indirect SCOMs

 - read()/write() interface now handle errors and retries

 - New ioctl() "raw" interface for use by debuggers
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com>
Reviewed-by: Alistair Popple <alistair@popple.id.au>

Add a few more register and bit definitions, also define and use
SCOM_READ_CMD (which is 0 but it makes the code clearer)
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com>

Use the proper annotated type __be32 and fixup the
accessor used for get_scom()
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com>

No functional changes
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com>

Otherwise, multiple clients can open the driver and attempt
to access the PIB at the same time, thus clobbering each other
in the process.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com>

fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:210:9: warning: cast to restricted __be32
fsi-core.c:606:15: warning: incorrect type in assignment (different base types)
fsi-core.c:606:15:    expected unsigned int [unsigned] [assigned] [usertype] smode
fsi-core.c:606:15:    got restricted __be32 [usertype] <noident>
fsi-core.c:492:28: warning: expression using sizeof(void)
fsi-core.c:520:29: warning: expression using sizeof(void)
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:682:19: warning: cast to restricted __be32
fsi-core.c:706:24: warning: incorrect type in assignment (different base types)
fsi-core.c:706:24:    expected unsigned int [unsigned] [usertype] llmode
fsi-core.c:706:24:    got restricted __be32 [usertype] <noident>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

fsi-master-hub.c:128:13: warning: incorrect type in assignment (different base types)
fsi-master-hub.c:128:13:    expected unsigned int [unsigned] [usertype] cmd
fsi-master-hub.c:128:13:    got restricted __be32 [usertype] <noident>
fsi-master-hub.c:208:13: warning: incorrect type in assignment (different base types)
fsi-master-hub.c:208:13:    expected restricted __be32 [addressable] [assigned] [usertype] reg
fsi-master-hub.c:208:13:    got int
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

fsi-sbefifo.c:547:58: warning: incorrect type in argument 2 (different base types)
fsi-sbefifo.c:547:58:    expected restricted __be32 [usertype] *word
fsi-sbefifo.c:547:58:    got unsigned int *<noident>
fsi-sbefifo.c:635:16: warning: incorrect type in assignment (different base types)
fsi-sbefifo.c:635:16:    expected unsigned int [unsigned] <noident>
fsi-sbefifo.c:635:16:    got restricted __be32 [usertype] <noident>
fsi-sbefifo.c:636:16: warning: incorrect type in assignment (different base types)
fsi-sbefifo.c:636:16:    expected unsigned int [unsigned] <noident>
fsi-sbefifo.c:636:16:    got restricted __be32 [usertype] <noident>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Spotted by kbuild-test-bot
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

This driver provides an in-kernel and a user API for accessing
the command FIFO of the SBE (Self Boot Engine) of the POWER9
processor, via the FSI bus.

It provides an in-kernel interface to submit command and receive
responses, along with a helper to locate and analyse the response
status block. It's a simple synchronous submit() type API.

The user interface uses the write/read interface that an earlier
version of this driver already provided, however it has some
specific limitations in order to keep the driver simple and
avoid using up a lot of kernel memory:

 - The user should perform a single write() with the command and
   a single read() to get the response (with a buffer big enough
   to hold the entire response).

 - On a write() the command is simply "stored" into a kernel buffer,
   it is submitted as one operation on the subsequent read(). This
   allows to have the code write directly from the FIFO into the user
   buffer and avoid hogging the SBE between the write() and read()
   syscall as it's critical that the SBE be freed asap to respond
   to the host. An extra write() will simply replace the previously
   written command.

 - A write of a single 4 bytes containing the value 0x52534554
   in big endian will trigger a reset request. No read is necessary,
   the write() call will return when the reset has been acknowledged
   or times out.

 - The command is limited to 4K bytes.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>
---

The PIB reset causes problems for the running P9 chip. The reset
shouldn't be performed by this driver.
Signed-off-by: Eddie James <eajames@linux.vnet.ibm.com>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

We currently use a spinlock (bit_lock) around operations that clock bits
out of the FSI bus, and a mutex to protect against simultaneous access
to the master.

This means that bit_lock isn't needed for mutual exlusion, only to
prevent timing issues when clocking bits out.

To reflect this, this change converts bit_lock to just the
local_irq_save/restore operation.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

Remove calls to the empty and useless fsi_master_gpio_error()
function, and report CRC errors as "FSI_ERR_NO_SLAVE" when
reading an all 1's response.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

The FSI protocol defines two modes of recovery from CRC errors,
this implements both:

 - If the device returns an ECRC (it detected a CRC error in the
   command), then we simply issue the command again.

 - If the master detects a CRC error in the response, we send
   an E_POLL command which requests a resend of the response
   without actually re-executing the command (which could otherwise
   have unwanted side effects such as dequeuing a FIFO twice).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>
---

Note: This was actually tested by removing some of my fixes, thus
causing us to hit occasional CRC errors during high LPC activity.

FSI CFAMs support shorter commands that use a relative (or same) address
as the last. This change introduces a last_addr to the master state, and
uses it for subsequent reads/writes, and performs relative addressing
when a subsequent read/write is in range.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

For implementing relative addressing mode, we'll need to build a command
that is coherent with CFAM state. To do that, include the
build_command_* functions in the locked section of read/write/term.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

Most SoC GPIO implementations, including the Aspeed one, have
synchronizers on the GPIO inputs. This means that the value
read from a GPIO is a couple of clocks old, from whatever clock
source feeds those synchronizers.

In practice, this means that in no-delay mode, we are using a
value that can potentially be a bit too old and too close to
the clock edge establishing the data on the other side of the link.

The voltage converters we use on some systems make this worse
and sensitive to things like voltage fluctuations etc... This is,
we believe, the cause of occasional CRC errors encountered during
heavy activity on the LPC bus.

This is fixed by introducing a dummy GPIO read before the actual
data read. It slows down SBEFIFO by about 15% (less than any delay
primitive) and the end result is so far solid.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

FSI_GPIO_DPOLL_CLOCKS is the number of clocks before sending
a DPOLL command after receiving a BUSY status. It should be
at least tSendDelay (16 clocks).

According to comments in the code, it needs to also be at least
21 clocks due to HW issues.

It's currently 100 clocks which impacts performances negatively
in some cases. Reduces it in half to 50 clocks which seems to
still be solid.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

FSI_GPIO_PRIME_SLAVE_CLOCKS is the number of clocks if the
"idle" phase between the end of a response and the beginning
of the next one. It corresponds to tSendDelay in the FSI
specification.

The default value in the slave is 16 clocks. 100 is way overkill
and significantly reduces the driver performance.

This changes it to 20 (which gives the HW a bit of margin still
just in case).
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

This adds support for an optional device-tree property that
makes the driver skip all the delays around clocking the
GPIOs and set it in the device-tree of common POWER9 based
OpenPower platforms.

This useful on chips like the AST2500 where the GPIO block is
running at a fairly low clock frequency (25Mhz typically). In
this case, the delays are unnecessary and due to the low
precision of the timers, actually quite harmful in terms of
performance.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

We currently sample the input data right after we toggle the
clock low, then high. The slave establishes the data on the
rising edge, so this is not ideal. We should sample it on
the low phase instead.

This currently works because we have an extra delay, but subsequent
patches will remove it.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: Christopher Bostic <cbostic@linux.vnet.ibm.com>
Tested-by: Joel Stanley <joel@jms.id.au>

Reduce time spent with interrupts disabled by limiting the critical
sections to bitbanging FSI symbols. We only need to ensure exclusive use
of the bus for an entire transfer, not that the transfer be performed in
atomic context.
Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

An observation from trace output of the existing FSI tracepoints was
that the remote device was sometimes reporting as busy. Add a new
tracepoint reporting the busy count in order to get a better grip on how
often this is the case.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Eddie James <eajames@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Joel Stanley <joel@jms.id.au>

Pull ARM SoC late updates from Olof Johansson:
 "This is a branch with a few merge requests that either came in late,
  or took a while longer for us to review and merge than usual and thus
  cut it a bit close to the merge window. We stage them in a separate
  branch and if things look good, we still send them up -- and that's
  the case here.

  This is mostly DT additions for Renesas platforms, adding IP block
  descriptions for existing and new SoCs.

  There are also some driver updates for Qualcomm platforms for SMEM/QMI
  and GENI, which is their generalized serial protocol interface"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (186 commits)
  soc: qcom: smem: introduce qcom_smem_virt_to_phys()
  soc: qcom: qmi: fix a buffer sizing bug
  MAINTAINERS: Update pattern for qcom_scm
  soc: Unconditionally include qcom Makefile
  soc: qcom: smem: check sooner in qcom_smem_set_global_partition()
  soc: qcom: smem: fix qcom_smem_set_global_partition()
  soc: qcom: smem: fix off-by-one error in qcom_smem_alloc_private()
  soc: qcom: smem: byte swap values properly
  soc: qcom: smem: return proper type for cached entry functions
  soc: qcom: smem: fix first cache entry calculation
  soc: qcom: cmd-db: Make endian-agnostic
  drivers: qcom: add command DB driver
  arm64: dts: renesas: salvator-common: Add ADV7482 support
  ARM: dts: r8a7740: Add CEU1
  ARM: dts: r8a7740: Add CEU0
  arm64: dts: renesas: salvator-common: enable VIN
  arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
  arm64: dts: renesas: r8a7795-es1: add CSI-2 node
  ...

Pull ARM SoC driver updates from Olof Johansson:
 "This contains platform-related driver updates for ARM and ARM64.

  Highlights:

   - ARM SCMI (System Control & Management Interface) driver cleanups

   - Hisilicon support for LPC bus w/ ACPI

   - Reset driver updates for several platforms: Uniphier,

   - Rockchip power domain bindings and hardware descriptions for
     several SoCs.

   - Tegra memory controller reset improvements"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (59 commits)
  ARM: tegra: fix compile-testing PCI host driver
  soc: rockchip: power-domain: add power domain support for px30
  dt-bindings: power: add binding for px30 power domains
  dt-bindings: power: add PX30 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3228
  dt-bindings: power: add binding for rk3228 power domains
  dt-bindings: power: add RK3228 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3128
  dt-bindings: power: add binding for rk3128 power domains
  dt-bindings: power: add RK3128 SoCs header for power-domain
  soc: rockchip: power-domain: add power domain support for rk3036
  dt-bindings: power: add binding for rk3036 power domains
  dt-bindings: power: add RK3036 SoCs header for power-domain
  dt-bindings: memory: tegra: Remove Tegra114 SATA and AFI reset definitions
  memory: tegra: Remove Tegra114 SATA and AFI reset definitions
  memory: tegra: Register SMMU after MC driver became ready
  soc: mediatek: remove unneeded semicolon
  soc: mediatek: add a fixed wait for SRAM stable
  soc: mediatek: introduce a CAPS flag for scp_domain_data
  soc: mediatek: reuse regmap_read_poll_timeout helpers
  ...

Pull ARM SoC device tree updates from Olof Johansson:
 "As always, a large number of DT updates. Too many to enumerate them
  all, but at a glance:

  New SoCs introduced in this release:

   - Amlogic:
      + Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some
        set top boxes and other products.

   - Mediatek:
      + MT7623A, which is a flavor of the MT7623 family with other
        on-chip ethernet options.

   - Qualcomm:
      + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845
        (Cortex-A75/A55 derivative) SoC that's one of the current
        high-end mobile SoCs.

        It's great to see mainline support for it. So far, you can't do
        much with it, since a lot of peripherals are not yet in the DTs
        but driver support for USB, GPU and other pieces are starting to
        trickle in. This might end up being a well-supported SoC
        upstream if the momentum keeps up.

   - Renesas:
      + R8A77990, a.k.a R-Car E3, a new automotive
        entertainment-targeted SoC. Currently only one Cortex-A53 CPU is
        enabled, we are eagerly awaiting more. So far, basic drivers
        such as serial, gpios, PMU and ethernet are enabled.
      + R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR
        GPU. Same here, basic set of drivers such as serial, gpios and
        ethernet enabled, and SMP support is also forthcoming.

   - STMicroelectronics:
      + STM32F469, very similar tih STM32F429 but with display support

  Enhancements to SoCs/platforms (DTS contents, some driver portions
  might not be in yet):
   - Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc
   - Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets
   - Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces
   - Marvell Berlin2CD: SMP support, thermal sensors
   - Mediatek MT7623: Highspeed DMA, audio support
   - Qualcomm IPQ8074 PCIe support, MSM8996 UFS support
   - Renesas: Watchdog and PMU support across many platforms
   - Rockchip RK3399: USB3 OTG support
   - Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3
   - STMicro STM32: Lots of peripherals added to STM32MP175C
   - Uniphier: Ethernet support

  New boards:
   - Allwinner A20: Olimex A20-SOM-EVB-eMMC variant
   - Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version)
   - Allwinner A33: Nintendo NES/SuperNES Classic Edition
   - Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune
   - Berlin2CD: Valve Steam Link
   - Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1
   - Broadcom: Raspberry Pi 3 B+
   - Mediatek MT7623N and MT7623A: reference boards
   - Meson 8M2: Tronsmart MXIII Plus
   - NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj
   - Qualcomm MSM8974: Sony Xperia Z1 Compact support
   - Qualcomm SDM845: MTP development board
   - Renesas: Ebisu R8A77990 board
   - Renesas RZ/G1C: iwg23s: iWave G235-SDB
   - TI am335x: Pocketbeagle support"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits)
  ARM: dts: aspeed: Fix hwrng register address
  arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog
  arm64: dts: sprd: Add GPIO and GPIO keys device nodes
  arm64: dts: sprd: fix typo in 'remote-endpoint'
  arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator
  arm64: dts: fix regulator property name for wlan pcie endpoint
  arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS
  ARM: dts: pxa3xx: fix MMC clocks
  ARM: pxa: dts: add pin definitions for extended GPIOs
  ARM: pxa: dts: add gpio-ranges to gpio controller
  ARM: dts: ipq8074: Enable few peripherals for hk01 board
  ARM: dts: ipq8074: Add pcie nodes
  ARM: dts: ipq8074: Add peripheral nodes
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
  ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
  ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
  ARM: dts: ipq4019: Change the max opp frequency
  ...

Pull ARM SoC platform updates from Olof Johansson:
 "Here are the main updates for SoC support (besides DT additions) for
  ARM 32- and 64-bit platforms. The branch also contains defconfig
  updates to turn on drivers and options as needed on the various
  platforms.

  The largest parts of the delta are from cleanups moving platform data
  and board file setup of TI platforms to ti-sysc bus drivers. There are
  also some sweeping changes of eeprom and nand setup on Davinci, i.MX
  and other platforms.

  Samsung is removing support for Exynos5440, which was an oddball SoC
  that hasn't been seen much use in designs.

  Renesas is adding support for new SoCs (R-Car E3, RZ/G1C and RZ/N1D).

  Linus Walleij is also removing support for ux500 (Sony Ericsson)
  U8540/9540 SoCs that never made it to significant mass production and
  products"

* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits)
  MAINTAINERS: add NXP linux team maillist as i.MX reviewer
  ARM: stm32: Don't select DMA unconditionally on STM32MP157C
  arm64: defconfig: Enable PCIe on msm8996 and db820c
  ARM: pxa3xx: enable external wakeup pins
  ARM: pxa: stargate2: use device properties for at24 eeprom
  arm64: defconfig: Enable HISILICON_LPC
  arm64: defconfig: enable drivers for Poplar support
  arm64: defconfig: Enable UFS on msm8996
  ARM: berlin: switch to SPDX license identifier
  arm: berlin: remove non-necessary flush_cache_all()
  ARM: berlin: extend BG2CD Kconfig entry
  OMAP: CLK: CLKSRC: Add suspend resume hooks
  ARM: AM43XX: Add functions to save/restore am43xx control registers
  ASoC: ams_delta: use GPIO lookup table
  ARM: OMAP1: ams-delta: add GPIO lookup tables
  bus: ti-sysc: Fix optional clocks array access
  ARM: OMAP2+: Make sure LOGICRETSTATE bits are not cleared
  ARM: OMAP2+: prm44xx: Inroduce cpu_pm notifiers for context save/restore
  ARM: OMAP2+: prm44xx: Introduce context save/restore for am43 PRCM IO
  ARM: OMAP2+: powerdomain: Introduce cpu_pm notifiers for context save/restore
  ...

Merging in defconfig updates. It's useful to keep them separate during
development but little point in merging them upstream on their own.

* next/defconfig: (40 commits)
  arm64: defconfig: Enable PCIe on msm8996 and db820c
  arm64: defconfig: Enable HISILICON_LPC
  arm64: defconfig: enable drivers for Poplar support
  arm64: defconfig: Enable UFS on msm8996
  arm64: defconfig: enable the Armada thermal driver
  ARM: multi_v7_defconfig: Enable RENESAS_WDT
  ARM: shmobile: defconfig: Enable RENESAS_WDT_GEN
  arm64: defconfig: enable R8A77990 SoC
  ARM: multi_v7_defconfig: Add STM32F7 I2C & STM32 USBPHYC support
  arm64: defconfig: Increase CMA size for VC4
  arm64: defconfig: enable rockchip efuse
  ARM: imx_v6_v7_defconfig: Select CONFIG_GPIO_MAX732X by default
  ARM: imx_v6_v7_defconfig: enable imx6sll by default
  arm64: defconfig: Enable CONFIG_SND_AUDIO_GRAPH_CARD
  arm64: defconfig: makes SND_SIMPLE_CARD to module
  ARM: multi_v7_defconfig: enable the Meson PWM controller
  arm: multi_v7_defconfig: enable the Amlogic Meson I2C driver
  arm64: defconfig: enable CONFIG_SPI_ARMADA_3700
  arm64: defconfig: Enable CONFIG_PINCTRL_MT7622 by default
  arm64: defconfig: Enable bluetooth USB support
  ...
Signed-off-by: Olof Johansson <olof@lixom.net>