- 06 Apr, 2023 28 commits
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Dmitry Baryshkov authored
Split pipe-dependent code from dpu_plane_sspp_atomic_update() into the separate function dpu_plane_sspp_update_pipe(). This is one of preparational steps to add r_pipe support. Reviewed-by:
Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280 Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/527337/ Link: https://lore.kernel.org/r/20230316161653.4106395-23-dmitry.baryshkov@linaro.orgSigned-off-by:
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Dmitry Baryshkov authored
The plane's clipped coordinates has already been validated against FB size in the drm_atomic_plane_check(). There is no need to check them again. Remove corresponding checks and inline dpu_plane_validate_src(). Reviewed-by:
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Dmitry Baryshkov authored
Now as all accesses to pipe_cfg and pstate have been cleaned, add struct dpu_hw_sspp_cfg to struct dpu_plane_state, so that dpu_plane_atomic_check() and dpu_plane_atomic_update() do not have a chance to disagree about src/dst rectangles (currently dpu_plane_atomic_check() uses unclipped rectangles, while dpu_plane_atomic_update() uses clipped rectangles calculated by drm_atomic_helper_check_plane_state()). Reviewed-by:
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Dmitry Baryshkov authored
Rework bandwidth/clock calculation functions to use mode directly rather than fetching it through the plane data. Reviewed-by:
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Dmitry Baryshkov authored
Rewrite dpu_plane's QoS related functions to take struct dpu_sw_pipe and struct dpu_format as arguments rather than fetching them from the pstate or drm_framebuffer. Reviewed-by:
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Dmitry Baryshkov authored
The helper drm_atomic_helper_check_plane_state() already checks whether the scaled and clipped plane falls into the CRTC visible region (and clears plane_state->visible if it doesn't). Drop the redundant check from dpu_crtc_atomic_check(). Reviewed-by:
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Dmitry Baryshkov authored
Move plane state updates from dpu_crtc_atomic_check() to the function where they belong: to dpu_plane_atomic_check(). Reviewed-by:
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Dmitry Baryshkov authored
The dpu_crtc_atomic_check() compares blending stage with DPU_STAGE_MAX (maximum amount of blending stages supported by the driver), however we should compare it against .max_mixer_blendstages, the maximum blend stage supported by the mixer. Reviewed-by:
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Dmitry Baryshkov authored
Neither source split nor multirect are properly supported at this moment. Both of these checks depend on normalized_zpos being equal for several planes (which is never the case for normalized zpos). Drop these checks to simplify dpu_crtc_atomic_check(). The actual support for either of these features is not removed from the backend code (sspp, ctl, etc). Reviewed-by:
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Dmitry Baryshkov authored
As struct dpu_hw_sspp_cfg describes only the source and destination rectangles, it is a software pipe configuration now. Rename it accordingly. Reviewed-by:
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Dmitry Baryshkov authored
Remove dpu_hw_fmt_layout instance from struct dpu_hw_sspp_cfg, leaving only src_rect and dst_rect. This way all the pipes used by the plane will have a common layout instance (as the framebuffer is shared between them), while still keeping a separate src/dst rectangle configuration for each pipe. Reviewed-by:
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Dmitry Baryshkov authored
Move stride programming to dpu_hw_sspp_setup_sourceaddress(), so that dpu_hw_sspp_setup_rects() programs only source and destination rectangles. Reviewed-by:
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Dmitry Baryshkov authored
Set SSPP_SRCn_ADDR registers to 0 while setting up solid fill, as we can not be sure that the previous address is still valid. Reviewed-by:
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Dmitry Baryshkov authored
There is no need to pass full dpu_hw_sspp_cfg instance to _dpu_hw_sspp_setup_scaler3, pass just struct dpu_format pointer. Reviewed-by:
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Dmitry Baryshkov authored
Where feasible, use dpu_sw_pipe rather than a combo of dpu_hw_sspp and multirect_index/_mode arguments. Reviewed-by:
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Dmitry Baryshkov authored
Wrap SSPP and multirect index/mode into a single structure that represents software view on the pipe used. Reviewed-by:
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Dmitry Baryshkov authored
There no more need for the dpu_plane_pipe() function, crtc code can access pstate->pipe_hw.idx directly. Reviewed-by:
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Dmitry Baryshkov authored
In preparation to adding fully virtualized planes, move struct dpu_hw_sspp instance from struct dpu_plane to struct dpu_plane_state, as it will become a part of state (variable, changes during runtime) rather than part of a plane (ideally should be statically allocated during boot). The sspp pointer is set at the dpu_plane_reset(), since this is the function which allocates the state. Once we have fully virtual plane<->SSPP relationship, the SSPP will be allocated dynamically in the dpu_plane_atomic_check() function. Reviewed-by:
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Dmitry Baryshkov authored
The pipe's layout is not cached, corresponding data structure is zeroed out each time in the dpu_plane_sspp_atomic_update(), right before the call to _dpu_plane_set_scanout() -> dpu_format_populate_layout(). Drop plane_addr comparison against previous layout and corresponding EAGAIN handling. Reviewed-by:
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Dmitry Baryshkov authored
As SSPP blocks are now visible through dpu_kms->rm.sspp_blocks, move SSPP debugfs creation from dpu_plane to dpu_kms. We are going to break the 1:1 correspondence between planes and SSPPs, so it makes no sense anymore to create SSPP debugfs entries in dpu_plane.c Reviewed-by:
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Dmitry Baryshkov authored
Follow the example of all other hw blocks and initialize SSPP blocks in Resource Manager. Reviewed-by:
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Dmitry Baryshkov authored
For all hardware blocks except SSPP the corresponding struct is named after the block. Rename dpu_hw_pipe (SSPP structure) to dpu_hw_sspp. Also rename struct dpu_hw_pipe_cfg to dpu_hw_sspp_cfg to follow this change. Reviewed-by:
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Leonard Lausen authored
Commit da7716a2 ("drm/msm/dpu: Add support for XR30 format") enabled support for the 10-bit XR30 color format but missed enabling support for the corresponding per-pixel alpha-blending AR30 color format. Declaring only XR30 but not AR30 color format support can trigger bugs in userspace. KDE KWin compositor versions prior to 5.27.3 for example prefer 10-bit color formats, rendering a 1cm^2 black box around the cursor due to missing per-pixel alpha-blending. Signed-off-by:
Leonard Lausen <leonard@lausen.nl> Reviewed-by:
Jessica Zhang <quic_jesszhan@quicinc.com> Tested-by: Jessica Zhang <quic_jesszhan@quicinc.com> # Trogdor (sc7180) Patchwork: https://patchwork.freedesktop.org/patch/527985/ Link: https://lore.kernel.org/r/6f33219dc848ccd7122bce6933338033aa18c33c@lausen.nlSigned-off-by:
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Kalyan Thota authored
Flush mechanism for DSPP blocks has changed in sc7280 family, it allows individual sub blocks to be flushed in coordination with master flush control. Representation: master_flush && (PCC_flush | IGC_flush .. etc ) This change adds necessary support for the above design. Changes in v1: - Few nits (Doug, Dmitry) - Restrict sub-block flush programming to dpu_hw_ctl file (Dmitry) Changes in v2: - Move the address offset to flush macro (Dmitry) - Separate ops for the sub block flush (Dmitry) Changes in v3: - Reuse the DPU_DSPP_xx enum instead of a new one (Dmitry) Changes in v4: - Use shorter version for unsigned int (Stephen) Changes in v5: - Spurious patch please ignore. Changes in v6: - Add SOB tag (Doug, Dmitry) Changes in v7: - Cache flush mask per dspp (Dmitry) - Few nits (Marijn) Changes in v8: - Few nits (Marijn) Changes in v9: - Use DSPP enum while accessing flush mask to make it readable (Dmitry) - Few nits (Dmitry) Changes in v10: - Fix white spaces in a separate patch (Dmitry) Changes in v11: - Define a macro for dspp flush selection (Marijn) - Few nits (Marijn) Changes in v12: - Minor comments (reorder macros and a condition) (Marijn) Signed-off-by:
Kalyan Thota <quic_kalyant@quicinc.com> Tested-by:
Douglas Anderson <dianders@chromium.org> Patchwork: https://patchwork.freedesktop.org/patch/520701/ Link: https://lore.kernel.org/r/1674814487-2112-1-git-send-email-quic_kalyant@quicinc.comSigned-off-by:
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Neil Armstrong authored
Document the DPU hardware found on the Qualcomm SM8550 platform. Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/517511/ Link: https://lore.kernel.org/r/20230103-topic-sm8550-upstream-mdss-dsi-v3-2-660c3bcb127f@linaro.org [DB: removed interconnect header inclusion] Signed-off-by:
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Jessica Zhang authored
Now that the TE setup has been moved to prepare_for_kickoff(), we have not prepare_commit() callbacks left. This makes dpu_encoder_prepare_commit() do nothing. Remove prepare_commit() from DPU driver. Changes in V3: - Reworded commit message to be more clear - Corrected spelling mistake in commit message Changes in V4: - Reworded commit message for clarity Signed-off-by:
Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/523606/ Link: https://lore.kernel.org/r/20230221184256.1436-4-quic_jesszhan@quicinc.com [DB: fixed merge conflict] Signed-off-by:
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Jessica Zhang authored
Currently, DPU will enable TE during prepare_commit(). However, this will cause a crash and reboot to sahara when trying to read/write to register in get_autorefresh_config(), because the core clock rates aren't set at that time. This used to work because phys_enc->hw_pp is only initialized in mode set [1], so the first prepare_commit() will return before any register read/write as hw_pp would be NULL. However, when we try to implement support for INTF TE, we will run into the clock issue described above as hw_intf will *not* be NULL on the first prepare_commit(). This is because the initialization of dpu_enc->hw_intf has been moved to dpu_encoder_setup() [2]. To avoid this issue, let's enable TE during prepare_for_kickoff() instead as the core clock rates are guaranteed to be set then. Depends on: "Implement tearcheck support on INTF block" [3] Changes in V3: - Added function prototypes - Reordered function definitions to make change more legible - Removed prepare_commit() function from dpu_encoder_phys_cmd Changes in V4: - Reworded commit message to be more specific - Removed dpu_encoder_phys_cmd_is_ongoing_pptx() prototype [1] https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L1109 [2] https://gitlab.freedesktop.org/drm/msm/-/blob/msm-next/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c#L2339 [3] https://patchwork.freedesktop.org/series/112332/Signed-off-by:
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Jessica Zhang authored
Add a NULL check before calling prepare_commit() in msm_atomic_commit_tail() Signed-off-by:
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- 03 Apr, 2023 2 commits
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Konrad Dybcio authored
The adreno_load_gpu() path is guarded by an error check on adreno_load_fw(). This function is responsible for loading Qualcomm-only-signed binaries (e.g. SQE and GMU FW for A6XX), but it does not take the vendor-signed ZAP blob into account. By embedding the SQE (and GMU, if necessary) firmware into the initrd/kernel, we can trigger and unfortunate path that would not bail out early and proceed with gpu->hw_init(). That will fail, as the ZAP loader path will not find the firmware and return back to adreno_load_gpu(). This error path involves pm_runtime_put_sync() which then calls idle() instead of suspend(). This is suboptimal, as it means that we're not going through the clean shutdown sequence. With at least A619_holi, this makes the GPU not wake up until it goes through at least one more start-fail-stop cycle. The pm_runtime_put_sync that appears in the error path actually does not guarantee that because of the earlier enabling of runtime autosuspend. Fix that by using pm_runtime_put_sync_suspend to force a clean shutdown. Test cases: 1. All firmware baked into kernel 2. error loading ZAP fw in initrd -> load from rootfs at DE start Both succeed on A619_holi (SM6375) and A630 (SDM845). Fixes: 0d997f95 ("drm/msm/adreno: fix runtime PM imbalance at gpu load") Signed-off-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by:
Johan Hovold <johan+linaro@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/530001/ Link: https://lore.kernel.org/r/20230330231517.2747024-1-konrad.dybcio@linaro.orgSigned-off-by:
Rob Clark <robdclark@chromium.org>
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Konrad Dybcio authored
Recently I contributed the switch to OPP API for all Adreno generations. I did however also skip over the fact that GPUs with a GMU don't specify a core clock of any kind in the GPU node. While that didn't break anything, it did introduce unwanted spam in the dmesg: adreno 5000000.gpu: error -ENOENT: _opp_set_clknames: Couldn't find clock with name: core_clk Guard the entire logic so that it's not used with GMU-equipped GPUs. Fixes: 9f251f93 ("drm/msm/adreno: Use OPP for every GPU generation") Signed-off-by:
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- 31 Mar, 2023 2 commits
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Konrad Dybcio authored
Add support for matching QFPROM fuse values to get the correct speed bin on A650 (SM8250) GPUs. Reviewed-by:
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Konrad Dybcio authored
Add support for matching QFPROM fuse values to get the correct speed bin on A640 (SM8150) GPUs. Reviewed-by:
Akhil P Oommen <quic_akhilpo@quicinc.com> Signed-off-by:
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- 30 Mar, 2023 1 commit
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Dmitry Baryshkov authored
Use adreno_fault_handler() to implement a5xx_fault_handler(). This enables devcoredump support on a5xx platforms, allowing one to capture the crashed GPU state at the time of context fault. Signed-off-by:
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- 28 Mar, 2023 7 commits
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Dmitry Baryshkov authored
Split the a6xx_fault_handler() into the generic adreno_fault_handler() and platform-specific parts. The adreno_fault_handler() can further be used by a5xx and hopefully by a4xx (at some point). Signed-off-by:
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Dmitry Baryshkov authored
The commit e25e92e0 ("drm/msm: devcoredump iommu fault support") enabled SMMU stalling to collect GPU state, but only for a6xx. It tied enabling the stall with tha per-instance pagetables creation. Since that commit SoCs with a5xx also gained support for adreno-smmu-priv. Move stalling into generic code and add corresponding resume_translation calls. Signed-off-by:
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Rob Clark authored
Drop our custom thing and switch to drm_crtc_next_vblank_start() for calculating the time of the start of the next vblank period. Signed-off-by:
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Rob Clark authored
Add a way for various userspace waits to signal urgency. Signed-off-by:
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Rob Clark authored
Track the nearest deadline on a fence timeline and set a timer to expire shortly before to trigger boost if the fence has not yet been signaled. v2: rebase Signed-off-by:
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Rob Clark authored
This series adds a deadline hint to fences, so realtime deadlines such as vblank can be communicated to the fence signaller for power/ frequency management decisions. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers See https://patchwork.freedesktop.org/series/93035/ This does not yet add any UAPI, although this will be needed in a number of cases: 1) Workloads "ping-ponging" between CPU and GPU, where we don't want the GPU freq governor to interpret time stalled waiting for GPU as "idle" time 2) Cases where the compositor is waiting for fences to be signaled before issuing the atomic ioctl, for example to maintain 60fps cursor updates even when the GPU is not able to maintain that framerate. Signed-off-by:
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Rob Clark authored
For an atomic commit updating a single CRTC (ie. a pageflip) calculate the next vblank time, and inform the fence(s) of that deadline. v2: Comment typo fix (danvet) v3: If there are multiple CRTCs, consider the time of the soonest vblank Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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