- 26 Jan, 2017 12 commits
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Linus Walleij authored
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Mika Westerberg authored
Currently we already have two pin configuration related callbacks available for GPIO chips .set_single_ended() and .set_debounce(). In future we expect to have even more, which does not scale well if we need to add yet another callback to the GPIO chip structure for each possible configuration parameter. Better solution is to reuse what we already have available in the generic pinconf. To support this, we introduce a new .set_config() callback for GPIO chips. The callback takes a single packed pin configuration value as parameter. This can then be extended easily beyond what is currently supported by just adding new types to the generic pinconf enum. If the GPIO driver is backed up by a pinctrl driver the GPIO driver can just assign gpiochip_generic_config() (introduced in this patch) to .set_config and that will take care configuration requests are directed to the pinctrl driver. We then convert the existing drivers over .set_config() and finally remove the .set_single_ended() and .set_debounce() callbacks. Suggested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Mika Westerberg authored
When a GPIO driver is backed by a pinctrl driver the GPIO driver sometimes needs to call the pinctrl driver to configure certain things, like whether the pin is used as input or output. In addition to this there are other configurations applicable to GPIOs such as setting debounce time of the GPIO. To support this we introduce a new function pinctrl_gpio_set_config() that can be used by gpiolib based driver to pass configuration requests to the backing pinctrl driver. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Mika Westerberg authored
The current pinconf packed format allows only 16-bit argument limiting the maximum value 65535. For most types this is enough. However, debounce time can be in range of hundreths of milliseconds in case of mechanical switches so we cannot represent the worst case using the current format. In order to support larger values change the packed format so that the lower 8 bits are used as type which leaves 24 bits for the argument. This allows representing values up to 16777215 and debounce times up to 16 seconds. We also convert the existing users to use 32-bit integer when extracting argument from the packed configuration value. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Arnd Bergmann authored
A cleanup caused a harmless warning: drivers/pinctrl/mvebu/pinctrl-kirkwood.c: In function 'kirkwood_pinctrl_probe': drivers/pinctrl/mvebu/pinctrl-kirkwood.c:460:19: error: unused variable 'res' [-Werror=unused-variable] The obvious fix is to remove the declaration of the now unused variable. Fixes: ad9ec4ec ("pinctrl: mvebu: switch drivers to generic simple mmio") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
This is less straight-forward than one would hope, as some banks only have 4 pins rather than 8, others are output only, yet more (W and X, already supported) are input-only, and in the case of the g4 SoC bank AC doesn't exist. Add some structs to describe the varying properties of different banks and integrate mechanisms to deny requests for unsupported configurations. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andrew Jeffery authored
Incorrect video output configuration bits were being tested on pins in GPIO banks AA and AB for the ROM{8,16} mux functions. The ROM{8,16} functions are the highest priority for the relevant pins and also the default function, so we require the relevant video output configuration be disabled to mux GPIO functionality. As the wrong bits were being tested a GPIO export would succeed but leave the pin in an unresponsive state (i.e. value updates were ignored). This misbehaviour was discovered as part of extending the GPIO controller's support to cover banks Y, Z, AA, AB and AC (AC in the case of the g5 SoC). Fixes: 6d329f14 ("pinctrl: aspeed-g4: Add mux configuration for all pins") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Joel Stanley authored
The Aspeed SoCs have more GPIOs than can be represented with A-Z. The documentation uses two letter names such as AA and AB, so make the names a three-character array in the bank struct to accommodate this. Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Julia Cartwright authored
The MSM pinctrl driver currently implements an irq_chip for handling GPIO interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. On real-time kernels, this fixes an OOPs which looks like the following, as reported by Brian Wrenn: kernel BUG at kernel/locking/rtmutex.c:1014! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: spidev_irq(O) smsc75xx wcn36xx [last unloaded: spidev] CPU: 0 PID: 1163 Comm: irq/144-mmc0 Tainted: G W O 4.4.9-linaro-lt-qcom #1 PC is at rt_spin_lock_slowlock+0x80/0x2d8 LR is at rt_spin_lock_slowlock+0x68/0x2d8 [..] Call trace: rt_spin_lock_slowlock rt_spin_lock msm_gpio_irq_ack handle_edge_irq generic_handle_irq msm_gpio_irq_handler generic_handle_irq __handle_domain_irq gic_handle_irq Reported-by: Brian Wrenn <dcbrianw@gmail.com> Tested-by: Brian Wrenn <dcbrianw@gmail.com> Signed-off-by: Julia Cartwright <julia@ni.com> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Marek Szyprowski authored
Return proper error code in case of memory allocation failure. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Marek Szyprowski authored
Memory subsystem already prints message about failed memory allocation, there is no need to do it in the drivers. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Marek Szyprowski authored
Add missing compatible id for Exynos3250 SoC to device tree docs. Exynos pin control driver supports it since commit d97f5b98 ("pinctrl: exynos: Add driver data for Exynos3250"). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 18 Jan, 2017 9 commits
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Wei Yongjun authored
It's not necessary to unregister pin controller device registered with devm_pinctrl_register() and using pinctrl_unregister() leads to a double free. Fixes: 3bfd4430 ("pinctrl: amd: Add support for additional GPIO") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Neil Armstrong authored
Add pinctrl functions for HDMI HPD pin and DDC pins on Amlogic Meson GXL and GXBB SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Krzysztof Kozlowski authored
Support for Exynos4415 is going away because there are no internal nor external users. Since commit 46dcf0ff ("ARM: dts: exynos: Remove exynos4415.dtsi"), the platform cannot be instantiated so remove also the drivers. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Colin Ian King authored
pin is an unsigned int and therefore can never be < 0 so this check is redundant. Remove the check and the associated dev_err error message. Fixes CoverityScan CID#1396438 ("Unsigned compared against 0") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Nishanth Menon <nm@ti.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
Add a simple regmap based pinctrl implementation for mvebu, for syscon based regmap drivers. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
Move the mvebu pinctrl drivers over to the generic simple mmio implementation, saving a substantial number of lines of code in the process. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
Provide a generic simple mmio-based probe function and methods, which pinctrl drivers can use to initialise the mvebu pinctrl subsystem. Most mvebu pinctrl drivers can use this. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
Provide per-control private data into each mvebu pinctrl method, which will allow us to provide some completely generic helpers without the global variable and per-instance function definitions that would be required when we have multiple pin controllers on a SoC. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Russell King authored
As the mvebu_mpp_ctrl structures contain function pointers, it is preferable for these to be made read-only to prevent the function pointers being modified. So make these const. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 17 Jan, 2017 5 commits
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Markus Elfring authored
Single characters should be put into a sequence. Thus use the corresponding function "seq_putc". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Markus Elfring authored
Strings which did not contain data format specifications should be put into a sequence. Thus use the corresponding function "seq_puts". This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. WARNING: void function return statements are not generally useful Thus remove such a statement in the affected function. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Markus Elfring authored
The script "checkpatch.pl" pointed information out like the following. WARNING: Possible unnecessary 'out of memory' message Thus fix the affected source code places. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Markus Elfring authored
* A multiplication for the size determination of a memory allocation indicated that an array data structure should be processed. Thus use the corresponding function "kmalloc_array". This issue was detected by using the Coccinelle software. * Replace the specification of a data structure by a pointer dereference to make the corresponding size determination a bit safer according to the Linux coding style convention. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 13 Jan, 2017 3 commits
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.11 - Add bias handling for non-GPIO pins for R-Car H3, - Add drive-strength and bias handling for R-Car M3-W, - Add CAN, CAN FD, MSIOF, and HSCIF pin groups for R-Car M3-W, - Add SDHI voltage switching for R-Car M2-N.
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Thierry Reding authored
The struct pinctrl_dev's node field is not properly set up, which means the .prev and .next fields will be NULL. That's not something that the linked list code can deal with, so extra care must be taken when using these fields. An example of this is introduced in commit 3429fb3c ("pinctrl: Fix panic when pinctrl devices with hogs are unregistered") where list_del() is made conditional on the pinctrl device being part of the pinctrl device list. This is to ensure that list_del() won't crash upon encountering a NULL pointer in .prev and/or .next. After initializing the list head there's no need to jump through these extra hoops and list_del() will work unconditionally. This is because the initialized list head points to itself and therefore the .prev and .next fields can be properly dereferenced. Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tony Lindgren authored
Commit df61b366af26 ("pinctrl: core: Use delayed work for hogs") caused a regression at least with sh-pfc that is also a GPIO controller as noted by Geert Uytterhoeven <geert@linux-m68k.org>. As the original pinctrl_register() has issues calling pin controller driver functions early before the controller has finished registering, we can't just revert commit df61b366af26. That would break the drivers using GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. So let's fix the issue with the following steps as a single patch: 1. Revert the late_init parts of commit df61b366af26. The late_init clearly won't work and we have to just give up on fixing pinctrl_register() for GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. 2. Split pinctrl_register() into two parts By splitting pinctrl_register() into pinctrl_init_controller() and pinctrl_create_and_start() we have better control over when it's safe to call pinctrl_create(). 3. Introduce a new pinctrl_register_and_init() function As suggested by Linus Walleij <linus.walleij@linaro.org>, we can just introduce a new function for the controllers that need pinctrl_create() called later. 4. Convert the four known problem cases to use new function Let's convert pinctrl-imx, pinctrl-single, sh-pfc and ti-iodelay to use the new function to fix the issues. The rest of the drivers can be converted later. Let's also update Documentation/pinctrl.txt accordingly because of the known issues with pinctrl_register(). Fixes: df61b366af26 ("pinctrl: core: Use delayed work for hogs") Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 11 Jan, 2017 7 commits
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Icenowy Zheng authored
V3s SoC features only a pin controller (for the lack of CPUs part). Add a driver for this controller. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Dan Carpenter authored
We accidentally deleted two tabs from the first line, but even with that fixed the conditions were not really kernel style. Put the && at the end of the line so we can align the condition clauses. Also add spaces around the "+" operator. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Fabio Estevam authored
Fix a typo in "Peripherals". Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Bjorn Andersson authored
Upon failing kzalloc() will print an error message in the log, so there's no need for additional printouts. Also standardizes the "!ptr" vs "ptr == NULL" while I'm touching those lines. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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David Lechner authored
This adds the pintrol-da850-pupd driver to the module device table so that udev will automatically bind the driver to the device. Signed-off-by: David Lechner <david@lechnology.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Andy Shevchenko authored
This simplifies error handling and allows us to drop error path handlers completely. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Mika Westerberg authored
This simplifies error handling and allows us to drop intel_pinctrl_remove() completely. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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- 09 Jan, 2017 4 commits
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Nishanth Menon authored
SoC family such as DRA7 family of processors have, in addition to the regular muxing of pins (as done by pinctrl-single), a separate hardware module called IODelay which is also expected to be configured. The "IODelay" module has it's own register space that is independent of the control module and the padconf register area. With recent changes to the pinctrl framework, we can now support this hardware with a reasonably minimal driver by using #pinctrl-cells, GENERIC_PINCTRL_GROUPS and GENERIC_PINMUX_FUNCTIONS. It is advocated strongly in TI's official documentation considering the existing design of the DRA7 family of processors during mux or IODelay reconfiguration, there is a potential for a significant glitch which may cause functional impairment to certain hardware. It is hence recommended to do as little of muxing as absolutely necessary without I/O isolation (which can only be done in initial stages of bootloader). NOTE: with the system wide I/O isolation scheme present in DRA7 SoC family, it is not reasonable to do stop all I/O operations for every such pad configuration scheme. So, we will let it glitch when used in this mode. Even with the above limitation, certain functionality such as MMC has mandatory need for IODelay reconfiguration requirements, depending on speed of transfer. In these cases, with careful examination of usecase involved, the expected glitch can be controlled such that it does not impact functionality. In short, IODelay module support as a padconf driver being introduced here is not expected to do SoC wide I/O Isolation and is meant for a limited subset of IODelay configuration requirements that need to be dynamic and whose glitchy behavior will not cause functionality failure for that interface. IMPORTANT NOTE: we take the approach of keeping LOCK_BITs cleared to 0x0 at all times, even when configuring Manual IO Timing Modes. This is done by eliminating the LOCK_BIT=1 setting from Step of the Manual IO timing Mode configuration procedure. This option leaves the CFG_* registers unprotected from unintended writes to the CTRL_CORE_PAD_* registers while Manual IO Timing Modes are configured. This approach is taken to allow for a generic driver to exist in kernel world that has to be used carefully in required usecases. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> [tony@atomide.com: updated to use generic pinctrl functions, added binding documentation, updated comments] Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tony Lindgren authored
If the pin controller driver is using devm_kzalloc, there may not be anything to do for dt_free_map. Let's make it optional to avoid unncessary boilerplate code. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Maxime Ripard authored
Now that we have a common pinctrl driver for all the sun5i SoCs, we can remove the old, separate drivers. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Maxime Ripard authored
The sun5i SoCs (A10s, A13, GR8) are all based on the same die fit in different packages. Hence, the pins and functions available are just the based on the same set, each SoC having a different subset. Introduce a common pinctrl driver that supports multiple variants to allow to put as much as we can in common. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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