- 15 Jul, 2024 1 commit
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Aurabindo Pillai authored
Increase the KMS minor version to indicate GFX12 DCC support since this contains a major change in how DCC is managed across IPs like GFX, DCN etc. This will be used mainly by userspace like Mesa to figure out DCC support on GFX12 hardware. v2: fix version number (Alex) Signed-off-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
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- 12 Jul, 2024 3 commits
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Alex Deucher authored
Fixes the indexing of the string array. Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Alex Deucher authored
Add new packet. Reviewed-by:
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Leo Li authored
This change caused PSR SU panels to not read from their remote fb, preventing us from entering self-refresh. It is a regression. This reverts commit eb6dfbb7. Signed-off-by:
Leo Li <sunpeng.li@amd.com> Acked-by:
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- 10 Jul, 2024 13 commits
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Alex Deucher authored
Enable it by default. Reviewed-by:
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YiPeng Chai authored
The problem case is as follows: 1. GPU A triggers a gpu ras reset, and GPU A drives GPU B to also perform a gpu ras reset. 2. After gpu B ras reset started, gpu B queried a DE data. Since the DE data was queried in the ras reset thread instead of the page retirement thread, bad page retirement work would not be triggered. Then even if all gpu resets are completed, the bad pages will be cached in RAM until GPU B's bad page retirement work is triggered again and then saved to eeprom. This patch can save the bad pages to eeprom in time after gpu ras reset is completed. v2: 1. Add the above description to code comments. 2. Reuse existing function. Signed-off-by:
YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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YiPeng Chai authored
Before uninstalling gpu driver, flush all cached ras bad pages to eeprom. v2: Put the same code into a function and reuse the function. Signed-off-by:
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Sunil Khatri authored
GFX ME right now is one but this could change in future SOC's. Use no of ME for GFX as start point for ME for compute for GFX12. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Acked-by:
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Aurabindo Pillai authored
To enable mesa to use display dcc, DM should expose them in the supported modifiers. Add the best (most efficient) modifiers first. Signed-off-by:
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Sunil Khatri authored
GFX ME right now is one but this could change in future SOC's. Use no of ME for GFX as start point for ME for compute for GFX11. Signed-off-by:
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Alex Deucher authored
Use the dev_info/err variants so we get per device logging in multi-GPU cases. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Sunil Khatri authored
GFX ME right now is one but this could change in future SOC's. Use no of ME for GFX as start point for ME for compute for GFX10. Signed-off-by:
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Danijel Slivka authored
Why: If the reg mmMP1_SMN_C2PMSG_90 is being written to during amdgpu driver load or driver unload, subsequent amdgpu driver load will fail at smu_hw_init. The default of mmMP1_SMN_C2PMSG_90 register at a clean environment is 0x1 and if value differs from expected, amdgpu driver load will fail. How to fix: Ignore the initial value in smu response register before the first smu message is sent,if smc in SMU_FW_INIT state, just proceed further to send the message. If register holds an unexpected value after smu message was sent set, smc_state to SMU_FW_HANG state and no further smu messages will be sent. v2: Set SMU_FW_INIT state at the start of smu hw_init/resume. Check smc_fw_state before sending smu message if in hang state skip sending message. Set SMU_FW_HANG only in case unexpected value is detected Signed-off-by:
Danijel Slivka <danijel.slivka@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Asad Kamal <asad.kamal@amd.com> Signed-off-by:
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Lijo Lazar authored
For SOCs with GFX v9.4.3, a VF may have multiple compute partitions. Fetch the partition information during init and initialize partition nodes. There is no support to switch partition mode in VF mode, hence disable the same. Signed-off-by:
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Gavin Wan authored
sdma has 2 instances in SRIOV cpx mode. Odd numbered VFs have sdma0/sdma1 instances. Even numbered vfs have sdma2/sdma3. For Even numbered vfs, the sdma2 & sdma3 (irq srouce id CLIENTID_SDMA2 and CLIENTID_SDMA3) should map to irq seq 0 & 1. Signed-off-by:
Gavin Wan <Gavin.Wan@amd.com> Reviewed-by:
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Alex Deucher authored
Switch to fist last for consistency. Reviewed-by:
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Alex Deucher authored
Evan is no longer maintaining powerplay and swsmu. Add Kenneth Feng as his replacement. Acked-by:
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- 08 Jul, 2024 23 commits
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Zhigang Luo authored
to avoid reading wrong WPTR from doorbell in sriov vf, set CP_HQD_PQ_DOORBELL_CONTROL.DOORBELL_MODE to 1 to read WPTR from MQD. Signed-off-by:
Zhigang Luo <Zhigang.Luo@amd.com> Acked-by:
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Kent Russell authored
Add "Series" to MI200 and MI300 to clarify that they represent the series of cards, and to more closely match the product information materials. This also matches other entries in this list Also correct a typo in the MI300 codename (Vangaram->Vanjaram) Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Yang Wang authored
add amdgpu ras 'event_state' sysfs device attribute support Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Li Ma authored
V1: This patch enables following UMD stable Pstates profile levels for power_dpm_force_performance_level interface. - profile_peak - profile_min_mclk - profile_min_sclk - profile_standard V2: Fix conflict with commit "drm/amd/pm: smu v14.0.4 reuse smu v14.0.0 dpmtable " V3: Add VCLK1 and DCLK1 support for SMU V14.0.1 And avoid to set VCLK1 and DCLK1 for SMU v14.0.0 Signed-off-by:
Li Ma <li.ma@amd.com> Reviewed-by:
Tim Huang <tim.huang@amd.com> Signed-off-by:
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Yang Wang authored
add amdgpu ras POSION_CONSUMPTION event id support. Signed-off-by:
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Stanley.Yang authored
GFX v9.4.4 uses mode1 reset to handle poison consumption. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
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Yang Wang authored
add amdgpu ras POSION_CREATION event id support. Signed-off-by:
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Yang Wang authored
v1: - use unified event id to manage ras events - add a new function amdgpu_ras_query_error_status_with_event() to accept event type as parameter. v2: add a warn log to show the location of function failure when calling amdgpu_ras_mark_event(). (Tao Zhou) v3: change RAS_EVENT_TYPE_ISR to RAS_EVENT_TYPE_FATAL. v4: rename amdgpu_ras_get_recovery_event() to amdgpu_ras_get_fatal_error_event(). Signed-off-by:
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Wayne Lin authored
[Why] In dm resume, we firstly restore dc state and do the mst resume for topology probing thereafter. If we change dpcd DP_MSTM_CTRL value after LT in mst reume, it will cause light up problem on the hub. [How] Revert commit 202dc359 ("drm/amd/display: Defer handling mst up request in resume"). And adjust the reason to trigger dc_link_detect by DETECT_REASON_RESUMEFROMS3S4. Cc: stable@vger.kernel.org Fixes: 202dc359 ("drm/amd/display: Defer handling mst up request in resume") Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Fangzhi Zuo <jerry.zuo@amd.com> Signed-off-by:
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Christian König authored
A gang submit won't work if the VMID is reserved and we can't flush out VM changes from multiple engines at the same time. Signed-off-by:
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Saleemkhan Jamadar authored
DPG mode is enabled for vcn and jpeg on VCN v4_0_5 Signed-off-by:
Saleemkhan Jamadar <saleemkhan.jamadar@amd.com> Reviewed-by:
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Yang Wang authored
remove redundant semicolons in RAS_EVENT_LOG to avoid code format check warning. Fixes: b712d7c2 ("drm/amdgpu: fix compiler 'side-effect' check issue for RAS_EVENT_LOG()") Signed-off-by:
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Frank Min authored
While moving buffer which has dcc tiling config, it is needed to restore its original dcc tiling. 1. extend copy flag to cover tiling bits 2. add logic to restore original dcc tiling config Signed-off-by:
Frank Min <Frank.Min@amd.com> Reviewed-by:
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Sunil Khatri authored
Add support of all the CP GFX queues for gfx12 ipdump to be used by devcoredump. Reviewed-by:
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Sunil Khatri authored
Add gfx12 support of CP queue registers for all queues to be used by devcoredump. Reviewed-by:
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Sunil Khatri authored
Enable redirection of irq for pagefaults for specific clients to avoid overflow without dropping interrupts. So here we redirect the interrupts to another IH ring i.e ring1 where only these interrupts are processed. Signed-off-by:
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Sunil Khatri authored
We need IH ring1 for handling the pagefault interrupts which over flow in default ring for specific usecases. Enable ring1 allows software to redirect high interrupts to ring1 from default IH ring. Signed-off-by:
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Yifan Zha authored
[Why] If VF request full GPU access and the request failed, the VF driver can get stuck accessing registers for an extended period during the unload of KMS. [How] Set no_hw_access flag when VF request for full GPU access fails This prevents further hardware access attempts, avoiding the prolonged stuck state. Signed-off-by:
Yifan Zha <Yifan.Zha@amd.com> Acked-by:
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Sunil Khatri authored
Add support of gfx12 ipdump print so devcoredump could trigger it to dump the captured registers in devcoredump. Reviewed-by:
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Sunil Khatri authored
Add general registers of gfx12 in ipdump for devcoredump support. Reviewed-by:
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Frank Min authored
update gfxhub client id for gfx12 Signed-off-by:
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Tim Huang authored
Certain call paths still load the SMU firmware for APUs, which needs to be skipped. Signed-off-by:
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YiPeng Chai authored
Sysfs node disable query error count during gpu reset. Signed-off-by:
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