- 14 Jan, 2023 17 commits
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Piergiorgio Beruto authored
Revert a wrong fix that was done during the review process. The intention was to substitute "if(ret < 0)" with "if(ret)". Unfortunately, the intended fix did not meet the code. Besides, after additional review, it was decided that "if(ret < 0)" was actually the right thing to do. Fixes: 8580e16c ("net/ethtool: add netlink interface for the PLCA RS") Signed-off-by:
Piergiorgio Beruto <piergiorgio.beruto@gmail.com> Reviewed-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
Eric Dumazet <edumazet@google.com> Link: https://lore.kernel.org/r/f2277af8951a51cfee2fb905af8d7a812b7beaf4.1673616357.git.piergiorgio.beruto@gmail.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
Michael Walle says: ==================== net: mdio: Continue separating C22 and C45 I've picked this older series from Andrew up and rebased it onto the latest net-next. This is the second patch set in the series which separates the C22 and C45 MDIO bus transactions at the API level to the MDIO bus drivers. ==================== Link: https://lore.kernel.org/r/20230112-net-next-c45-seperation-part-2-v1-0-5eeaae931526@walle.ccSigned-off-by:
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Andrew Lunn authored
The enetc MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. This driver is shared with the Felix DSA switch, so update that at the same time. Signed-off-by:
Michael Walle <michael@walle.cc> Signed-off-by:
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Andrew Lunn authored
The stmmac MDIO bus driver in variant gmac4 can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by:
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Andrew Lunn authored
The stmicro stmmac xgmac2 MDIO bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by:
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Andrew Lunn authored
The microchip lan743x MDIO bus driver can perform both C22 and C45 transfers in some variants. Create separate functions for each and register the C45 versions using the new API calls where appropriate. Signed-off-by:
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Andrew Lunn authored
The mediatek bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls. Signed-off-by:
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Andrew Lunn authored
The ipq4019 driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new driver API calls. Signed-off-by:
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Andrew Lunn authored
The aspeed MDIO bus driver can perform both C22 and C45 transfers. Modify the existing C45 functions to take the devad as a parameter, and remove the wrappers so there are individual C22 and C45 functions. Add the C45 functions to the new API calls. Signed-off-by:
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Andrew Lunn authored
The MDIO mux broadcom iproc can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls. Signed-off-by:
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Andrew Lunn authored
The MDIO over I2C bus driver can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions using the new API calls. Signed-off-by:
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Andrew Lunn authored
The cavium IP can perform both C22 and C45 transfers. Create separate functions for each and register the C45 versions in both the octeon and thunder bus driver. Signed-off-by:
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Bin Chen authored
Add basic DCB IEEE support. This includes support for ETS, max-rate, and DSCP to user priority mapping. DCB may be configured using iproute2's dcb command. Example usage: dcb ets set dev $dev tc-tsa 0:ets 1:ets 2:ets 3:ets 4:ets 5:ets \ 6:ets 7:ets tc-bw 0:0 1:80 2:0 3:0 4:0 5:0 6:20 7:0 dcb maxrate set dev $dev tc-maxrate 1:1000bit And DCB configuration can be shown using: dcb ets show dev $dev dcb maxrate show dev $dev Signed-off-by:Bin Chen <bin.chen@corigine.com> Signed-off-by:
Simon Horman <simon.horman@corigine.com> Link: https://lore.kernel.org/r/20230112121102.469739-1-simon.horman@corigine.comSigned-off-by:
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Lorenzo Bianconi authored
Similar to MTK Wireless Ethernet Dispatcher (WED) MCU rx queue, we do not need to protect WED MCU tx queue with a spin lock since the tx queue is accessed in the two following routines: - mtk_wed_wo_queue_tx_skb(): it is run at initialization and during mt7915 normal operation. Moreover MCU messages are serialized through MCU mutex. - mtk_wed_wo_queue_tx_clean(): it runs just at mt7915 driver module unload when no more messages are sent to the MCU. Remove tx queue spinlock. Signed-off-by:
Lorenzo Bianconi <lorenzo@kernel.org> Link: https://lore.kernel.org/r/7bd0337b2a13ab1a63673b7c03fd35206b3b284e.1673515140.git.lorenzo@kernel.orgSigned-off-by:
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Jon Maxwell authored
In ip6_dst_gc() replace: if (entries > gc_thresh) With: if (entries > ops->gc_thresh) Sending Ipv6 packets in a loop via a raw socket triggers an issue where a route is cloned by ip6_rt_cache_alloc() for each packet sent. This quickly consumes the Ipv6 max_size threshold which defaults to 4096 resulting in these warnings: [1] 99.187805] dst_alloc: 7728 callbacks suppressed [2] Route cache is full: consider increasing sysctl net.ipv6.route.max_size. . . [300] Route cache is full: consider increasing sysctl net.ipv6.route.max_size. When this happens the packet is dropped and sendto() gets a network is unreachable error: remaining pkt 200557 errno 101 remaining pkt 196462 errno 101 . . remaining pkt 126821 errno 101 Implement David Aherns suggestion to remove max_size check seeing that Ipv6 has a GC to manage memory usage. Ipv4 already does not check max_size. Here are some memory comparisons for Ipv4 vs Ipv6 with the patch: Test by running 5 instances of a program that sends UDP packets to a raw socket 5000000 times. Compare Ipv4 and Ipv6 performance with a similar program. Ipv4: Before test: MemFree: 29427108 kB Slab: 237612 kB ip6_dst_cache 1912 2528 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 2881 3990 192 42 2 : tunables 0 0 0 During test: MemFree: 29417608 kB Slab: 247712 kB ip6_dst_cache 1912 2528 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 44394 44394 192 42 2 : tunables 0 0 0 After test: MemFree: 29422308 kB Slab: 238104 kB ip6_dst_cache 1912 2528 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 3048 4116 192 42 2 : tunables 0 0 0 Ipv6 with patch: Errno 101 errors are not observed anymore with the patch. Before test: MemFree: 29422308 kB Slab: 238104 kB ip6_dst_cache 1912 2528 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 3048 4116 192 42 2 : tunables 0 0 0 During Test: MemFree: 29431516 kB Slab: 240940 kB ip6_dst_cache 11980 12064 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 3048 4116 192 42 2 : tunables 0 0 0 After Test: MemFree: 29441816 kB Slab: 238132 kB ip6_dst_cache 1902 2432 256 32 2 : tunables 0 0 0 xfrm_dst_cache 0 0 320 25 2 : tunables 0 0 0 ip_dst_cache 3048 4116 192 42 2 : tunables 0 0 0 Tested-by:
Andrea Mayer <andrea.mayer@uniroma2.it> Signed-off-by:
Jon Maxwell <jmaxwell37@gmail.com> Reviewed-by:
David Ahern <dsahern@kernel.org> Link: https://lore.kernel.org/r/20230112012532.311021-1-jmaxwell37@gmail.comSigned-off-by:
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Keith Busch authored
The details of the iov_iter types are appropriately abstracted, so there's no need to check for specific type fields. Just let the abstractions handle it. This is preparing for io_uring/net's io_send to utilize the more efficient ITER_UBUF. Signed-off-by:
Keith Busch <kbusch@kernel.org> Reviewed-by:
Jens Axboe <axboe@kernel.dk> Link: https://lore.kernel.org/r/20230111184245.3784393-1-kbusch@meta.comSigned-off-by:
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Anand Moon authored
Fix compatible string for RV1126 gmac, and constrain it to be compatible with Synopsys dwmac 4.20a. fix below warning $ make CHECK_DTBS=y rv1126-edgeble-neu2-io.dtb arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb: ethernet@ffc40000: compatible: 'oneOf' conditional failed, one must be fixed: ['rockchip,rv1126-gmac', 'snps,dwmac-4.20a'] is too long 'rockchip,rv1126-gmac' is not one of ['rockchip,rk3568-gmac', 'rockchip,rk3588-gmac'] Fixes: b36fe2f4 ("dt-bindings: net: rockchip-dwmac: add rv1126 compatible") Reviewed-by:Jagan Teki <jagan@edgeble.ai> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Anand Moon <anand@edgeble.ai> Link: https://lore.kernel.org/r/20230111172437.5295-1-anand@edgeble.aiSigned-off-by:
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- 13 Jan, 2023 23 commits
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Yunhui Cui authored
Add 2 tracepoints to monitor the tcp/udp traffic of per process and per cgroup. Regarding monitoring the tcp/udp traffic of each process, there are two existing solutions, the first one is https://www.atoptool.nl/netatop.php. The second is via kprobe/kretprobe. Netatop solution is implemented by registering the hook function at the hook point provided by the netfilter framework. These hook functions may be in the soft interrupt context and cannot directly obtain the pid. Some data structures are added to bind packets and processes. For example, struct taskinfobucket, struct taskinfo ... Every time the process sends and receives packets it needs multiple hashmaps,resulting in low performance and it has the problem fo inaccurate tcp/udp traffic statistics(for example: multiple threads share sockets). We can obtain the information with kretprobe, but as we know, kprobe gets the result by trappig in an exception, which loses performance compared to tracepoint. We compared the performance of tracepoints with the above two methods, and the results are as follows: ab -n 1000000 -c 1000 -r http://127.0.0.1/index.html without trace: Time per request: 39.660 [ms] (mean) Time per request: 0.040 [ms] (mean, across all concurrent requests) netatop: Time per request: 50.717 [ms] (mean) Time per request: 0.051 [ms] (mean, across all concurrent requests) kr: Time per request: 43.168 [ms] (mean) Time per request: 0.043 [ms] (mean, across all concurrent requests) tracepoint: Time per request: 41.004 [ms] (mean) Time per request: 0.041 [ms] (mean, across all concurrent requests It can be seen that tracepoint has better performance. Signed-off-by:
Yunhui Cui <cuiyunhui@bytedance.com> Signed-off-by:
Xiongchun Duan <duanxiongchun@bytedance.com> Reviewed-by:
Steven Rostedt (Google) <rostedt@goodmis.org> Signed-off-by:
David S. Miller <davem@davemloft.net>
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David S. Miller authored
Daniele Palmas says: ==================== net: add tx packets aggregation to ethtool and rmnet Hello maintainers and all, this patchset implements tx qmap packets aggregation in rmnet and generic ethtool support for that. Some low-cat Thread-x based modems are not capable of properly reaching the maximum allowed throughput both in tx and rx during a bidirectional test if tx packets aggregation is not enabled. I verified this problem with rmnet + qmi_wwan by using a MDM9207 Cat. 4 based modem (50Mbps/150Mbps max throughput). What is actually happening is pictured at https://drive.google.com/file/d/1gSbozrtd9h0X63i6vdkNpN68d-9sg8f9/view Testing with iperf TCP, when rx and tx flows are tested singularly there's no issue in tx and minor issues in rx (not able to reach max throughput). When there are concurrent tx and rx flows, tx throughput has an huge drop. rx a minor one, but still present. The same scenario with tx aggregation enabled is pictured at https://drive.google.com/file/d/1jcVIKNZD7K3lHtwKE5W02mpaloudYYih/view showing a regular graph. This issue does not happen with high-cat modems (e.g. SDX20), or at least it does not happen at the throughputs I'm able to test currently: maybe the same could happen when moving close to the maximum rates supported by those modems. Anyway, having the tx aggregation enabled should not hurt. The first attempt to solve this issue was in qmi_wwan qmap implementation, see the discussion at https://lore.kernel.org/netdev/20221019132503.6783-1-dnlplm@gmail.com/ However, it turned out that rmnet was a better candidate for the implementation. Moreover, Greg and Jakub suggested also to use ethtool for the configuration: not sure if I got their advice right, but this patchset add also generic ethtool support for tx aggregation. The patches have been tested mainly against an MDM9207 based modem through USB and SDX55 through PCI (MHI). v2 should address the comments highlighted in the review: the implementation is still in rmnet, due to Subash's request of keeping tx aggregation there. v3 fixes ethtool-netlink.rst content out of table bounds and a W=1 build warning for patch 2. v4 solves a race related to egress_agg_params. ==================== Signed-off-by:
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Daniele Palmas authored
Add support for ETHTOOL_COALESCE_TX_AGGR for configuring the tx aggregation settings. Signed-off-by:
Daniele Palmas <dnlplm@gmail.com> Signed-off-by:
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Daniele Palmas authored
Add tx packets aggregation. Bidirectional TCP throughput tests through iperf with low-cat Thread-x based modems revelead performance issues both in tx and rx. The Windows driver does not show this issue: inspecting USB packets revealed that the only notable change is the driver enabling tx packets aggregation. Tx packets aggregation is by default disabled and can be enabled by increasing the value of ETHTOOL_A_COALESCE_TX_MAX_AGGR_FRAMES. The maximum aggregated size is by default set to a reasonably low value in order to support the majority of modems. This implementation is based on patches available in Code Aurora repositories (msm kernel) whose main authors are Subash Abhinov Kasiviswanathan <subashab@codeaurora.org> Sean Tranchetti <stranche@codeaurora.org> Signed-off-by:
Subash Abhinov Kasiviswanathan <quic_subashab@quicinc.com> Signed-off-by:
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Daniele Palmas authored
Add the following ethtool tx aggregation parameters: ETHTOOL_A_COALESCE_TX_AGGR_MAX_BYTES Maximum size in bytes of a tx aggregated block of frames. ETHTOOL_A_COALESCE_TX_AGGR_MAX_FRAMES Maximum number of frames that can be aggregated into a block. ETHTOOL_A_COALESCE_TX_AGGR_TIME_USECS Time in usecs after the first packet arrival in an aggregated block for the block to be sent. Signed-off-by:
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David S. Miller authored
Arun Ramadoss says: ==================== net: dsa: microchip: add PTP support for KSZ9563/KSZ8563 and LAN937x KSZ9563/KSZ8563 and LAN937x switch are capable for supporting IEEE 1588 PTP protocol. LAN937x has the same PTP register set similar to KSZ9563, hence the implementation has been made common for the KSZ switches. KSZ9563 does not support two step timestamping but LAN937x supports both. Tested the 1step & 2step p2p timestamping in LAN937x and p2p1step timestamping in KSZ9563. This patch series is based on the Christian Eggers PTP support for KSZ9563. Applied the Christian patch and updated as per the latest refactoring of KSZ series code. The features added on top are PTP packet Interrupt implementation based on nested handler, LAN937x two step timestamping and programmable per_out pins. Link: https://www.spinics.net/lists/netdev/msg705531.html Patch v7 -> v8 - set skb->ip_summed = CHECKSUM_NONE after updating the checksum Patch v6 -> v7 - Corrected the misplaced spaces and tabs - Added mutex lock in do_aux_work - Replaced 0/1 with false/true for ts_en - SKB_TX_INPROGRESS flag is set before dsa_enqueue_skb - Removed the fallthrough keyword - pdelay_resp header correction is performed based on KSZ_SKB_CB(skb)->update_correction instead of clone Patch v5 -> v6 - Rebased to latest net-next and renamed from RFC to patch net-next. Patch v4 -> v5 - Replaced irq_domain_add_simple with irq_doamin_add_linear - Used the helper diff_by_scaled_ppm() for adjfine. Patch v3 -> v4 - removed IRQF_TRIGGER_FALLING from the request_threaded_irq of ptp msg - addressed review comments on patch 10 periodic output - added sign off in patch 6 & 9 - reverted to set PTP_1STEP bit for lan937x which is missed during v3 regression Patch v2-> v3 - used port_rxtstamp for reconstructing the absolute timestamp instead of tagger function pointer. - Reverted to setting of 802.1As bit. Patch v1 -> v2 - GPIO perout enable bit is different for LAN937x and KSZ9x. Added new patch for configuring LAN937x programmable pins. - PTP enabled in hardware based on both tx and rx timestamping of all the user ports. - Replaced setting of 802.1AS bit with P2P bit in PTP_MSG_CONF1 register. RFC v2 -> Patch v1 - Changed the patch author based on past patch submission - Changed the commit message prefix as net: dsa: microchip: ptp Individual patch changes are listed in correspondig commits. RFC v1 -> v2 - Added the p2p1step timestamping and conditional execution of 2 step for LAN937x only. - Added the periodic output support ==================== Signed-off-by:
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Arun Ramadoss authored
There is difference in implementation of per_out pins between KSZ9563 and LAN937x. In KSZ9563, Timestamping control register (0x052C) bit 6, if 1 - timestamp input and 0 - trigger output. But it is opposite for LAN937x 1 - trigger output and 0 - timestamp input. As per per_out gpio pins, KSZ9563 has four Led pins and two dedicated gpio pins. But in LAN937x dedicated gpio pins are removed instead there are up to 10 LED pins out of which LED_0 and LED_1 can be mapped to PTP tou 0, 1 or 2. This patch sets the bit 6 in 0x052C register and configure the LED override and source register for LAN937x series of switches alone. Signed-off-by:
Arun Ramadoss <arun.ramadoss@microchip.com> Signed-off-by:
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Arun Ramadoss authored
LAN937x series of switches support 2 step timestamping mechanism. There are timestamp correction calculation performed in ksz_rcv_timestamp and ksz_xmit_timestamp which are applicable only for p2p1step. To check whether the 2 step is enabled or not in tag_ksz.c introduced the helper function in taggger_data to query it from ksz_ptp.c. Based on whether 2 step is enabled or not, timestamp calculation are performed. Signed-off-by:
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Arun Ramadoss authored
There are two programmable pins available for Trigger output unit to generate periodic pulses. This patch add verify_pin for the available 2 pins and configure it with respect to GPIO index for the TOU unit. Tested using testptp ./testptp -i 0 -L 0,2 ./testptp -i 0 -d /dev/ptp0 -p 1000000000 ./testptp -i 1 -L 1,2 ./testptp -i 1 -d /dev/ptp0 -p 100000000 Signed-off-by:
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Christian Eggers authored
LAN937x and KSZ PTP supported switches has Three Trigger output unit. This TOU can used to generate the periodic signal for PTP. TOU has the cycle width register of 32 bit in size and period width register of 24 bit, each value is of 8ns so the pulse width can be maximum 125ms. Tested using ./testptp -d /dev/ptp0 -p 1000000000 -w 100000000 for generating the 10ms pulse width Signed-off-by:
Christian Eggers <ceggers@arri.de> Co-developed-by:
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Christian Eggers authored
For PDelay_Resp messages we will likely have a negative value in the correction field. The switch hardware cannot correctly update such values (produces an off by one error in the UDP checksum), so it must be moved to the time stamp field in the tail tag. Format of the correction field is 48 bit ns + 16 bit fractional ns. After updating the correction field, clone is no longer required hence it is freed. Signed-off-by:
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Christian Eggers authored
This patch adds the routines for transmission of ptp packets. When the ptp pdelay_req packet to be transmitted, it uses the deferred xmit worker to schedule the packets. During irq_setup, interrupt for Sync, Pdelay_req and Pdelay_rsp are enabled. So interrupt is triggered for all three packets. But for p2p1step, we require only time stamp of Pdelay_req packet. Hence to avoid posting of the completion from ISR routine for Sync and Pdelay_resp packets, ts_en flag is introduced. This controls which packets need to processed for timestamp. After the packet is transmitted, ISR is triggered. The time at which packet transmitted is recorded to separate register. This value is reconstructed to absolute time and posted to the user application through socket error queue. Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
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Christian Eggers authored
Rx Timestamping is done through 4 additional bytes in tail tag. Whenever the ptp packet is received, the 4 byte hardware time stamped value is added before 1 byte tail tag. Also, bit 7 in tail tag indicates it as PTP frame. This 4 byte value is extracted from the tail tag and reconstructed to absolute time and assigned to skb hwtstamp. If the packet received in PDelay_Resp, then partial ingress timestamp is subtracted from the correction field. Since user space tools expects to be done in hardware. Signed-off-by:
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Christian Eggers authored
For P2P delay measurement, the ingress time stamp of the PDelay_Req is required for the correction field of the PDelay_Resp. The application echoes back the correction field of the PDelay_Req when sending the PDelay_Resp. Some hardware (like the ZHAW InES PTP time stamping IP core) subtracts the ingress timestamp autonomously from the correction field, so that the hardware only needs to add the egress timestamp on tx. Other hardware (like the Microchip KSZ9563) reports the ingress time stamp via an interrupt and requires that the software provides this time stamp via tail-tag on tx. In order to avoid introducing a further application interface for this, the driver can simply emulate the behavior of the InES device and subtract the ingress time stamp in software from the correction field. On egress, the correction field can either be kept as it is (and the time stamp field in the tail-tag is set to zero) or move the value from the correction field back to the tail-tag. Changing the correction field requires updating the UDP checksum (if UDP is used as transport). Signed-off-by:
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Arun Ramadoss authored
PTP Interrupt mask and status register differ from the global and port interrupt mechanism by two methods. One is that for global/port interrupt enabling we have to clear the bit but for ptp interrupt we have to set the bit. And other is bit12:0 is reserved in ptp interrupt registers. This forced to not use the generic implementation of global/port interrupt method routine. This patch implement the ptp interrupt mechanism to read the timestamp register for sync, pdelay_req and pdelay_resp. Signed-off-by:
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Christian Eggers authored
This patch is used for reconstructing the absolute time from the 32bit hardware time stamping value. The do_aux ioctl is used for reading the ptp hardware clock and store it to global variable. The timestamped value in tail tag during rx and register during tx are 32 bit value (2 bit seconds and 30 bit nanoseconds). The time taken to read entire ptp clock will be time consuming. In order to speed up, the software clock is maintained. This clock time will be added to 32 bit timestamp to get the absolute time stamp. Signed-off-by:
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Arun Ramadoss authored
When the PTP is enabled in hardware bit 6 of PTP_MSG_CONF1 register, the transmit frame needs additional 4 bytes before the tail tag. It is needed for all the transmission packets irrespective of PTP packets or not. The 4-byte timestamp field is 0 for frames other than Pdelay_Resp. For the one-step Pdelay_Resp, the switch needs the receive timestamp of the Pdelay_Req message so that it can put the turnaround time in the correction field. Since PTP has to be enabled for both Transmission and reception timestamping, driver needs to track of the tx and rx setting of the all the user ports in the switch. Two flags hw_tx_en and hw_rx_en are added in ksz_port to track the timestampping setting of each port. When any one of ports has tx or rx timestampping enabled, bit 6 of PTP_MSG_CONF1 is set and it is indicated to tag_ksz.c through tagger bytes. This flag adds 4 additional bytes to the tail tag. When tx and rx timestamping of all the ports are disabled, then 4 bytes are not added. Tested using hwstamp -i <interface> Signed-off-by:
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Christian Eggers authored
This patch adds the routine for get_ts_info, hwstamp_get, set. This enables the PTP support towards userspace applications such as linuxptp. Signed-off-by:
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Christian Eggers authored
This patch implement routines (adjfine, adjtime, gettime and settime) for manipulating the chip's PTP clock. It registers the ptp caps to posix clock register. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Reviewed-by:
Jacob Keller <jacob.e.keller@intel.com> Signed-off-by:
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Jakub Kicinski authored
Emeel Hakim says: ==================== Add support to offload macsec using netlink update This series adds support for offloading macsec as part of the netlink update routine, command example: $ ip link set link eth2 macsec0 type macsec offload mac The above is done using the IFLA_MACSEC_OFFLOAD attribute hence the second patch of dumping this attribute as part of the macsec dump. ==================== Link: https://lore.kernel.org/r/20230111150210.8246-1-ehakim@nvidia.comSigned-off-by:
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Emeel Hakim authored
Support dumping offload netlink attribute in macsec's device attributes dump. Change macsec_get_size to consider the offload attribute in the calculations of the required room for dumping the device netlink attributes. Signed-off-by:
Emeel Hakim <ehakim@nvidia.com> Reviewed-by:
Sabrina Dubroca <sd@queasysnail.net> Signed-off-by:
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Emeel Hakim authored
Add support for changing Macsec offload selection through the netlink layer by implementing the relevant changes in macsec_changelink. Since the handling in macsec_changelink is similar to macsec_upd_offload, update macsec_upd_offload to use a common helper function to avoid duplication. Example for setting offload for a macsec device: ip link set macsec0 type macsec offload mac Signed-off-by: -
Lukas Bulwahn authored
While reviewing dependencies in some Kconfig files, I noticed the redundant dependency "depends on PCI && PCI_MSI". The config PCI_MSI has always, since its introduction, been dependent on the config PCI. So, it is sufficient to just depend on PCI_MSI, and know that the dependency on PCI is implicitly implied. Reduce the dependencies of some network driver configs. No functional change and effective change of Kconfig dependendencies. Signed-off-by:
Lukas Bulwahn <lukas.bulwahn@gmail.com> Acked-by:
Dimitris Michailidis <dmichail@fungible.com> Link: https://lore.kernel.org/r/20230111125855.19020-1-lukas.bulwahn@gmail.comSigned-off-by:
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