- 19 Feb, 2018 40 commits
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Alex Deucher authored
Expose power via hwmon. Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Alex Deucher authored
Expose vddgfx and vddnb via hwmon. Acked-by:
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Alex Deucher authored
Return an error if the user tried to check or set the fan parameters while the card is powered down (e.g., on a PX/HG system for example). This makes the fan consistent with the temperature stuff. Acked-by:
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Christian König authored
Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by:
Monk Liu <monk.liu@amd.com> Signed-off-by:
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Rex Zhu authored
in populate_single_graphic_level for smu7 Reviewed-by:
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Rex Zhu authored
Move configurable profiling parameters to struct profile_mode_setting and initialize current_profile_setting. Reviewed-by:
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Rex Zhu authored
As not support per DPM level optimization, so delete activity_target array. Reviewed-by:
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Rex Zhu authored
And not support perDPM level optimization on Polaris, so delete sclk activity_target array. Reviewed-by:
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Andrey Grodzovsky authored
Dead code, looks obsolete. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
They seem to be obsolete. Signed-off-by:
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Harry Wentland authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Signed-off-by:
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John Barberiz authored
- Sequencing bug of not resetting delay on disconnect to default values Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Mikita Lipski authored
Remove aux engine register programming,when freeing the engine as it was a temporary workaround. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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John Barberiz authored
Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Leo (Sunpeng) Li authored
Fix: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c: In function ‘dce110_blank_stream’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:1008:31: error: unused variable ‘params’ [-Werror=unused-variable] struct encoder_unblank_param params = { { 0 } }; Signed-off-by:Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by:
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Charlene Liu authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Geling Li authored
Signed-off-by:
Geling Li <geling.li@amd.com> Reviewed-by:
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Krunoslav Kovac authored
Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Charlene Liu authored
Signed-off-by:
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Dmytro Laktyushkin authored
Directly editing pipe config outside of formula is error prone and results in higher clocks being used when splitting. For this reason we reverted to using bounding box hacking to split. Since sometimes this erroneusly results in higher dpm being required we unhack the bounding box and recalculate to allow dpm0 is possible. Side effect is we will lose some stutter efficiency in non dpm0 cases. This is not a big concern since increased stutter efficiency saves an order of magnitude less power than lower dpm. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Arun Pandey authored
Signed-off-by:
Arun Pandey <Arun.Pandey@amd.com> Reviewed-by:
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Charlene Liu authored
Signed-off-by:
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Yongqiang Sun authored
Use tg count in resource pool for further reference. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Lock top_pipe when doing update plane addr for split pipe freesync case Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Harry Wentland authored
There's no good place in DC to cover all place where stream signal should be updated. update_stream_signal depends on timing which comes from DM. Signed-off-by:
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Leo (Sunpeng) Li authored
If crc is disabled, early return when getting crc's. That way, we avoid reading extra registers within the pflip high irq. Signed-off-by:
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Yongqiang Sun authored
Signed-off-by:
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Ken Chalmers authored
Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Signed-off-by:
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Duke Du authored
Signed-off-by:
Duke Du <Duke.Du@amd.com> Signed-off-by:
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Harry Wentland authored
We're currently not using this. v2: More files and includes to remove. Signed-off-by:
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Alex Deucher authored
The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by:
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Alex Deucher authored
This way we can make all of the IP specific functions static, and we only need a single entry point into the PSP IP modules. Reviewed-by:
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Christian König authored
Instead of repeating this multiple times. Signed-off-by:
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Christian König authored
Reserve VA space at the top for older generations as well. Signed-off-by:
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Christian König authored
1MB should be more than enough, currently we use about 8K. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
Samuel Li <Samuel.Li@amd.com> Acked-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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Samuel Li authored
Add display to the name for consistency. Signed-off-by:
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