- 20 Mar, 2024 40 commits
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Anthony Koo authored
[WHY & HOW] Add new counters in the shared IPS firmware state. Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicholas Kazlauskas authored
[WHY] To log commit states and when we transition in/out of allow and idle states and the caller. [HOW] Add a new logging helper and wrap idle optimization calls to receive the caller. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Acked-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Muhammad Ahmed authored
[HOW] Add debug key to allow disabling dtbclk Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Tao Zhou authored
Let kfd interrupt handler process it. v2: return 0 instead of 1 for fed error. drop the usage of strcmp in interrupt handler. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Tao Zhou authored
Replace it with related interface in gfxhub functions. v2: replace node id with xcc id. get node id for query_utcl2_poison_status Signed-off-by: -
Sunil Khatri authored
Add relevant ringbuffer information such as rptr, wptr,rb mask, ring name, ring size and also the rings content for each ring on a gpu reset. Signed-off-by:
Sunil Khatri <sunil.khatri@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Roman Li authored
[WHY] Incorrect function name in function banner. [HOW] Correct name and brief description. Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Aurabindo Pillai <aurabindo.pillai@amd.com> Acked-by:
Roman Li <roman.li@amd.com> Tested-by:
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Sunil Khatri authored
Add page fault information to the devcoredump. Output of devcoredump: **** AMDGPU Device Coredump **** version: 1 kernel: 6.7.0-amd-staging-drm-next module: amdgpu time: 29.725011811 process_name: soft_recovery_p PID: 1720 Ring timed out details IP Type: 0 Ring Name: gfx_0.0.0 [gfxhub] Page fault observed Faulty page starting at address: 0x0000000000000000 Protection fault status register: 0x301031 VRAM is lost due to GPU reset! Signed-off-by:
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Tao Zhou authored
Implement it for gfxhub 1.0 and 1.2. v2: input logical xcc id for poison query interface. Signed-off-by:
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Tao Zhou authored
Add UCE and FED bit definitions. Signed-off-by:
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Aurabindo Pillai authored
Add DML2 compilation rule in the Makefile. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
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Sunil Khatri authored
Currently page fault information is stored per vm and which could be freed or stale during reset. Add it pagefault information in the vm_manager which is a global space for vm's and remains valid across. Signed-off-by:
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Aurabindo Pillai authored
[WHAT] Add DML2 pipe and config struct forward declaration as a preparation for DML2. Reviewed-by:
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Gabe Teeger authored
This reverts commit e2fdd5c5 ("drm/amd/display: Add left edge pixel for YCbCr422/420 + ODM pipe split") Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
George Shen <george.shen@amd.com> Reviewed-by:
Jun Lei <jun.lei@amd.com> Acked-by:
Wayne Lin <wayne.lin@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Tested-by:
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George Shen authored
[WHY] Currently 3-tap chroma subsampling is used for YCbCr422/420. When ODM pipesplit is used, pixels on the left edge of ODM slices need one extra pixel from the right edge of the previous slice to calculate the correct chroma value. Without this change, the chroma value is slightly different than expected. This is usually imperceptible visually, but it impacts test pattern CRCs for compliance test automation. [HOW] Update logic to use the register for adding extra left edge pixel for YCbCr422/420 ODM cases. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Martin Leung authored
why and how: causes black screen on PNP on DCN 3.5 This reverts commit f30a3bea ("drm/amd/display: Exit idle optimizations before HDCP execution") Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
Martin Leung <martin.leung@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[WHY] PSP can access DCN registers during command submission and we need to ensure that DCN is not in PG before doing so. [HOW] Add a callback to DM to lock and notify DC for idle optimization exit. It can't be DC directly because of a potential race condition with the link protection thread and the rest of DM operation. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Reviewed-by:
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Ma Jun authored
OD is not supported on Arcturus, so the OD table should not be used. Signed-off-by:
Ma Jun <Jun.Ma2@amd.com> Acked-by:
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Le Ma authored
To fix the entity rq NULL issue. This setting has been moved to upper level. Fixes: b7043800 ("drm/amdgpu: move buffer funcs setting up a level") Signed-off-by:
Le Ma <le.ma@amd.com> Reviewed-by:
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Leo Ma authored
[Why] When mode switching is triggered there is momentary noise visible on some HDMI TV or displays. [How] Wait for 2 frames to make sure we have enough time to send out AV mute and sink receives a full frame. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Leo Ma <hanghong.ma@amd.com> Tested-by:
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Wenjing Liu authored
This reverts commit 340383c7 ("drm/amd/display: Remove pixle rate limit for subvp") [why] The original commit causes a regression when subvp is applied on ODM required 8k60hz timing. The display shows black screen on boot. The issue can be recovered with hotplug. It also causes MPO to fail. We will temprarily revert this commit and investigate the root cause further. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Lang Yu authored
Ready now. Remove this workaround. This reverts commit d40f6213. Signed-off-by:
Lang Yu <Lang.Yu@amd.com> Tested-by:
Alan Liu <haoping.liu@amd.com> Acked-by:
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Ma Jun authored
This patch causes the following iounmap erorr and calltrace iounmap: bad address 00000000d0b3631f The original patch was unjustified because amdgpu_device_fini_sw() will always cleanup the rmmio mapping. This reverts commit eb4f1398. Signed-off-by:
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Allen Pan authored
[How] Check wheather state is NULL before releasing it. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Allen Pan <allen.pan@amd.com> Tested-by:
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Rodrigo Siqueira authored
[WHY & HOW] If the display is null when creating an HDCP session, return a proper error code. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Tested-by:
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Wenjing Liu authored
[WHY] Odm update is doubled buffered. We need to wait for ODM update to be completed before optimizing bandwidth or programming new udpates. [HOW] implement wait_for_odm_update_pending_complete function to wait for: 1. odm configuration update is no longer pending in timing generator. 2. no pending dpg pattern update for each active OPP. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Wenjing Liu authored
[WHY] On DCN32 we support dynamic ODM even when OTG is blanked. When ODM configuration is dynamically changed and the OTG is on blank pattern, we will need to reprogram OPP's test pattern based on new ODM configuration. Therefore we need to lock the OTG pipe to avoid temporary corruption when we are reprogramming OPP blank patterns. [HOW] Add a new interdependent update lock implementation to lock all enabled OTG pipes even when there is no plane on the OTG for DCN32. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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ChunTao Tso authored
[WHY] The original coasting vtotal is 2 bytes, and it need to be amended to 4 bytes because low hz case. [HOW] Amend coasting vtotal from 2 bytes to 4 bytes. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
ChunTao Tso <chuntao.tso@amd.com> Tested-by:
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Nicholas Kazlauskas authored
[WHY] We still had an instance of get_idle_state checking the PMFW scratch register instead of the actual idle allow signal. [HOW] Replace it with the SW state check for whether we had allowed idle through notify_idle. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Wenjing Liu authored
[WHY] When committing an update with ODM combine change when the plane is removing or already removed, we fail to detect odm change in pipe update flags. This has caused mismatch between new dc state and the actual hardware state, because we missed odm programming. [HOW] - Detect odm change even for otg master pipe without a plane. - Update odm config before calling program pipes for pipe with planes. The commit also updates blank pattern programming when odm is changed without plane. This is because number of OPP is changed when ODM combine is changed. Blank pattern is per OPP so we will need to reprogram OPP based on the new pipe topology. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Dillon Varone <dillon.varone@amd.com> Acked-by:
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Dillon Varone authored
[WHY & HOW] DPPCLK ranges should be obtained from the SMU when available. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Ryan Lin authored
[WHY] Some eDP panels' ext caps don't write initial values. The value of dpcd_addr (0x317) can be random and the backlight control interface will be incorrect. [HOW] Add new panel patches to remove sink ext caps. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org # 6.5.x Cc: Tsung-hua Lin <tsung-hua.lin@amd.com> Cc: Chris Chi <moukong.chi@amd.com> Reviewed-by:
Ryan Lin <tsung-hua.lin@amd.com> Tested-by:
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Josip Pavic authored
[WHY] It's beneficial for ABM to know when new frame data are available. [HOW] Add new condition to allow dirty rects to be sent to DMUB when ABM is active. ABM will use this as a signal that a new frame has arrived. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Josip Pavic <josip.pavic@amd.com> Tested-by:
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Sohaib Nadeem authored
[WHY]: Increasing min DCFCLK addresses underflow issues that occur when phantom pipe is turned on for some Sub-Viewport configs [HOW]: dcn32_override_min_req_dcfclk is added to override DCFCLK value in dml1_validate when subviewport is being used. Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Sohaib Nadeem <sohaib.nadeem@amd.com> Tested-by:
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Hawking Zhang authored
Do not load/invoke display TA if display hardware is not available. Signed-off-by:
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Prike Liang authored
Fix the KGQ fallback function name, as this will help differentiate the failure in the KCQ enablement. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Ma Jun authored
Check the validity of overdriver power limit before using it. Fixes: 7968e974 ("drm/amdgpu/pm: Fix the power1_min_cap value") Signed-off-by:
Lazar Lijo <lijo.lazar@amd.com> Suggested-by:
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Ma Jun authored
Because powerplay_table initialization is skipped under sriov case, We check and set default lower and upper OD value if powerplay_table is NULL. Fixes: 7968e974 ("drm/amdgpu/pm: Fix the power1_min_cap value") Signed-off-by:
Yin Zhenguo <zhenguo.yin@amd.com> Suggested-by:
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ZhenGuo Yin authored
[Why] RLCG interface returns "out-of-range" error under SRIOV VF when accessing PF-only registers. [How] Skip access PF-only registers on gfx10/gfxhub2_1 under SRIOV. Acked-by:
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Ahmad Rehman authored
In passthrough environment, when amdgpu is reloaded after unload, mode-1 is triggered after initializing the necessary IPs, That init does not include KFD, and KFD init waits until the reset is completed. KFD init is called in the reset handler, but in this case, the zone device and drm client is not initialized, causing app to create kernel panic. v2: Removing the init KFD condition from amdgpu_amdkfd_drm_client_create. As the previous version has the potential of creating DRM client twice. v3: v2 patch results in SDMA engine hung as DRM open causes VM clear to SDMA before SDMA init. Adding the condition to in drm client creation, on top of v1, to guard against drm client creation call multiple times. Signed-off-by:
Ahmad Rehman <Ahmad.Rehman@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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