- 14 Mar, 2018 40 commits
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Harry Wentland authored
Signed-off-by:
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Oak Zeng authored
This is preparation for sharing client ID definitions between amdgpu and amdkfd Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Bw spreadsheet was updated while dce_calcs was not Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Yongqiang Sun authored
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 1 set dispclk to request value. Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 0 set dispclk to request value. v2: squash in !DCN build fix Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Samson Tam authored
Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Shirish S authored
The order of planes is given by the order they are enumerated by kms. Planes with a higher ID appears above planes with a lower ID. Currently the planes are enumerated in the wrong order, putting the nv12 only plane after the two RGBA planes. This patch corrects the plane enumeration order such that all the overlay planes are initialized first then the primary planes. Due to this change in order the dc_add_plane_to_context() shall receive the planes in reverse order hence this patch reverses the parsing of planes in DM side itself. v2: drop local reverse macro for upstream Signed-off-by:
Shirish S <shirish.s@amd.com> Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Vitaly Prosyak authored
Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Tony Cheng authored
Signed-off-by:
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Anthony Koo authored
Time stamping will be part of surface, and will be updated when address is flipped. FreeSync parameters will be attached to stream, as it adjusts the timing dynamically. Signed-off-by:
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Anthony Koo authored
Stats will be used for debug purposes Signed-off-by:
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Eric Yang authored
The work around for hw bug causes S3 resume failure. Don't execute disable vga logic if not in vga mode. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Mikita Lipski authored
Initializing ABM and DMCU modules for dce 80/81/83/100 as in DCE110 Adding constructors and destructors for each module. Adding register list for DMCU in dce80 as some registers are missing in dce80 from the basic list. DMCU is never used, so it would not have any functional impact. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
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Krunoslav Kovac authored
In MPO scenario when playing SDR clip in HDR desktop mode, Win is boosting desktop and requests driver to boost MPO. But driver boosting is currently done in regamma which is stream property and thus shared between grph and video. Redesigning the boosting in RV: use CM_HDR_MULT register which was added for this scenario. It also has the benefit that it can be done in HIRQL. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
Use DC_LOGGER macro for logs. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
These MACROS are only being used by a few files but gets pulled in by dc.h Signed-off-by:
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Yongqiang Sun authored
This change make sure bandwidth is set properly. For increase bandwidth, set bandwidth before backend and front end programming. For decrease bandwidth, set bandwidth after. To avoid smu hang when reboot and dpms due to 0 disp clk, keep min disp clock as 100Mhz. Signed-off-by:
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Eric Yang authored
Per discussion with VBIOS team, the orginal check is not correct in all cases on latest VBIOS. Additional check is needed. This change should maintain old behaviour on older VBIOS. Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Bhawanpreet Lakha authored
HW Engineer's Notes: During switch from vga->extended, if we set the VGA_TEST_ENABLE and then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly. Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset VGA_TEST_ENABLE, to leave it in the same state as before. Signed-off-by:
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Jerry (Fangzhi) Zuo authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Yongqiang Sun authored
300Mhz disp clk limit was a workaround that was fixed in SMU and is no longer needed. Signed-off-by:
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Leo (Sunpeng) Li authored
DRM's documentation for the color transform matrix does not specify whether the values are in signed-magnitude, or 2's complement. Therefore, it was assumed to use 2's complement. However, existing usermode implementations use signed-magnitude. Therefore, conform to existing standards, and convert to 2's complement internally. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Add null check for stream update Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
Fix bug and make changes from review 132656 Signed-off-by:
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SivapiriyanKumarasamy authored
Avoid hanging DMCU by setting abm level only when OTG unblanked Signed-off-by:
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Leo (Sunpeng) Li authored
Should return -ENOMEM when allocation fails. Also, just return the error code instead of using a variable. Signed-off-by:
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Leo (Sunpeng) Li authored
While checking plane states for updates during atomic check, we create dc_plane_states in preparation. These dc states should be freed if something errors. Although the input transfer function is also freed by dc_plane_state_release(), we should free it (on error) under the same scope as where it is created. Signed-off-by:
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Harry Wentland authored
They were used by amdgpu_dm at some point but since it has its own amdgpu_dm_connector now these aren't needed anymore. Signed-off-by:
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Alex Deucher authored
Save/restore the backlight level scratch register in S3/S4 so the backlight level comes back at the previously requested level. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=199047 Fixes: 4ec6ecf4 (drm/amdgpu: drop scratch regs save and restore from S3/S4 handling) Acked-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Christian König authored
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the hardware was done with the buffere. Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
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Christian König authored
We unmapped imported DMA-bufs when the GEM handle was dropped, not when the hardware was done with the buffere. Signed-off-by:
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Christian König authored
Drop the "kernel" and sg parameter and give the BO type to create explicit to amdgpu_bo_create instead of figuring it out from the parameters. Signed-off-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Christian König authored
Just set the GTT domain as mandatory, so that the BO is validated into it on first use. This allows us to setup the sg table later on. Signed-off-by:
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Christian König authored
Instead of moving this to the SYSTEM domain just drop the backing store and let the resulting allocation be freed. Signed-off-by:
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Christian König authored
Better to set this with all other fields as well. Signed-off-by:
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Christian König authored
Instead of calculating the size in bytes just to recalculate the number of pages from it pass the BO directly to the function. Signed-off-by:
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Christian König authored
Allows us to gut a BO of it's backing store when the driver says that it isn't needed any more. Signed-off-by:
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Monk Liu authored
this patch actually refactor mailbox implmentations, and all below changes are needed together to fix all those mailbox handshake issues exposured by heavey TDR test. 1)refactor all mailbox functions based on byte accessing for mb_control reason is to avoid touching non-related bits when writing trn/rcv part of mailbox_control, this way some incorrect INTR sent to hypervisor side could be avoided, and it fixes couple handshake bug. 2)trans_msg function re-impled: put a invalid logic before transmitting message to make sure the ACK bit is in a clear status, otherwise there is chance that ACK asserted already before transmitting message and lead to fake ACK polling. (hypervisor side have some tricks to workaround ACK bit being corrupted by VF FLR which hase an side effects that may make guest side ACK bit asserted wrongly), and clear TRANS_MSG words after message transferred. 3)for mailbox_flr_work, it is also re-worked: it takes the mutex lock first if invoked, to block gpu recover's participate too early while hypervisor side is doing VF FLR. (hypervisor sends FLR_NOTIFY to guest before doing VF FLR and sentds FLR_COMPLETE after VF FLR done, and the FLR_NOTIFY will trigger interrupt to guest which lead to mailbox_flr_work being invoked) This can avoid the issue that mailbox trans msg being cleared by its VF FLR. 4)for mailbox_rcv_irq IRQ routine, it should only peek msg and schedule mailbox_flr_work, instead of ACK to hypervisor itself, because FLR_NOTIFY msg sent from hypervisor side doesn't need VF's ACK (this is because VF's ACK would lead to hypervisor clear its trans_valid/msg, and this would cause handshake bug if trans_valid/msg is cleared not due to correct VF ACK but from a wrong VF ACK like this "FLR_NOTIFY" one) This fixed handshake bug that sometimes GUEST always couldn't receive "READY_TO_ACCESS_GPU" msg from hypervisor. 5)seperate polling time limite accordingly: POLL ACK cost no more than 500ms POLL MSG cost no more than 12000ms POLL FLR finish cost no more than 500ms 6) we still need to set adev into in_gpu_reset mode after we received FLR_NOTIFY from host side, this can prevent innocent app wrongly succesed to open amdgpu dri device. FLR_NOFITY is received due to an IDLE hang detected from hypervisor side which indicating GPU is already die in this VF. v2: use MACRO as the offset of mailbox_control register don't test if NOTIFY_CMPL event in rcv_msg since it won't recieve that message anymore Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Pixel Ding <Pixel.Ding@amd.com> Signed-off-by:
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Monk Liu authored
mailbox registers can be accessed with a byte boundry according to BIF team, so this patch prepares register byte access and will be used by following patches. Actually, for mailbox registers once the byte field is touched even not changed, the mailbox behaves, so we need the byte width accessing to those sort of regs. Signed-off-by:
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Hawking Zhang authored
The vram type for dGPU is stored in umc_info while sys mem type for APU is stored in integratedsysteminfo Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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