Merge tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX DT bindings for 6.1:

- Add compatible for new boards: Kontron BL i.MX8MM OSM-S, MSC
  SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier, i.MX8M Mini Gateworks
  GW7904 board, i.MX8DXL EVK Board.
- Add add interconnect property for i.MX8MP various blk-ctrl devices.
- Add i.MX8MP HDMI HDCP and HRV power domain DT IDs.
- Add bindings for i.MX93 SRC and MEDIAMIX blk-ctrl.
- A minor style fix on i.MX8MM clock binding header.

* tag 'imx-bindings-6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  dt-bindings: arm: imx: update fsl.yaml for imx8dxl
  dt-bindings: firmware: add missing resource IDs for imx8dxl
  dt-bindings: arm: Add i.MX8M Mini Gateworks GW7904 board
  dt-bindings: soc: add i.MX93 mediamix blk ctrl
  dt-bindings: soc: add i.MX93 SRC
  dt-bindings: mfd: syscon: Add i.MX93 blk ctrl system registers
  dt-bindings: arm: fsl: Add MSC SM2S-IMX8PLUS SoM and SM2-MB-EP1 Carrier
  dt-bindings: arm: fsl: Add Kontron BL i.MX8MM OSM-S board
  dt-bindings: arm: fsl: Rename compatibles for Kontron i.MX8MM SoM/board
  dt-bindings: soc: imx: add i.MX8MP vpu blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MM vpu blk ctrl
  dt-bindings: soc: imx: drop minItems for i.MX8MM vpu blk ctrl
  dt-bindings: power: imx8mp-power: add HDMI HDCP/HRV
  dt-bindings: arm: fsl: imx6ul-kontron: Update bindings
  dt-bindings: clk: imx8mm: don't use multiple blank lines
  dt-bindings: soc: imx: add interconnect property for i.MX8MP hsio blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MP hdmi blk ctrl
  dt-bindings: soc: imx: add interconnect property for i.MX8MP media blk ctrl

Link: https://lore.kernel.org/r/20220918092806.2152700-1-shawnguo@kernel.orgSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

arm64: tegra: Device tree changes for v6.1-rc1

These changes enable PCI, Ethernet and HDA support on Jetson AGX Orin.
DMA support is enabled for I2C on a number of SoC generations and the
Google Pixel C (a.k.a. Smaug) device receives Bluetooth and Wi-Fi
support.

Other than that this also contains some minor cleanups and fixes.

* tag 'tegra-for-6.1-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Add GPCDMA support for Tegra I2C
  arm64: tegra: Add iommus for HDA on Tegra234
  arm64: tegra: Enable HDA node for Jetson AGX Orin
  arm64: tegra: Add context isolation domains on Tegra234
  arm64: tegra: Fixup iommu-map property formatting
  arm64: dts: tegra: smaug: Add Wi-Fi node
  arm64: dts: tegra: smaug: Add Bluetooth node
  arm64: tegra: Enable MGBE on Jetson AGX Orin Developer Kit
  arm64: tegra: Add MGBE nodes on Tegra234
  arm64: tegra: Fix up compatible for Tegra234 GPCDMA
  arm64: tegra: Enable PCIe slots in P3737-0000 board
  arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT
  arm64: tegra: Add regulators required for PCIe

Link: https://lore.kernel.org/r/20220916101957.1635854-5-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'tegra-for-6.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v6.1-rc1

Adds device tree bindings for the MGBE found on Tegra234 SoCs, as well
as stream IDs for the shared host1x context devices.

* tag 'tegra-for-6.1-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: Add Host1x context stream IDs on Tegra234
  dt-bindings: net: Add Tegra234 MGBE

Link: https://lore.kernel.org/r/20220916101957.1635854-4-thierry.reding@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

AT91 DT for v6.1 #2

It contains:
- new SAMA5D3 based board, namely SAMA5D3-EDS
- adjustments to pass the DT binding validations
- disable AES on some LAN966 based boards as they are reserverd by
  secure OS

* tag 'at91-dt-6.1-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties
  ARM: dts: at91: Add `atmel,usart-mode` required property to serial nodes
  ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1
  ARM: dts: at91: sama7g5: Swap rx and tx for spi11
  dts: arm: at91: Add SAMA5D3-EDS Board
  dt-bindings: arm: at91: Add info on SAMA5D3-EDS
  ARM: dts: lan966x: disable aes

Link: https://lore.kernel.org/r/20220916105407.1287452-1-claudiu.beznea@microchip.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

i.MX8DXL is a device targeting the automotive and industrial market
segments. The chip is designed to achieve both high performance and
low power consumption. It has a dual (2x) Cortex-A35 processor.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add the missing resource IDs for imx8dxl.
Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add DT compatible string for i.MX8M Mini based Gateworks GW7904 board.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add DT bindings for i.MX93 MEDIAMIX BLK CTRL.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add bindings for i.MX93 System Reset Controller(SRC). SRC supports
resets and power gating for mixes.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Document i.MX93 BLK CTRL system registers.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add DT compatible strings for a combination of the 14N0600E variant of
the Avnet (MSC branded) SM2S-IMX8PLUS SoM on it's own and in combination
with the SM2-MB-EP1 carrier board.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add bindings for the Kontron BL i.MX8MM OSM-S board.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

This updates the bindings in order to use names for the boards that
follow the latest convention used by Kontron marketing.

By updating we make sure, that we can maintain this more easily in
future and make sure that the proper devicetree can be selected for
the hardware.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

i.MX8MP VPU blk ctrl module has similar design as i.MX8MM, so reuse
the i.MX8MM VPU blk ctrl yaml file. And add description for the items.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

i.MX8MM VPU support NoC QoS setting, so add interconnect property
for i.MX8MM VPU blk ctrl
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

minItems and maxItems are set as the same value. In such case minItems is
not necessary. So drop it.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Add i.MX8MP HDMI HDCP and HRV entries.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

This updates the bindings in order to simplify the devicetree
structure and to add names for the boards that follow the latest
convention used by Kontron marketing.

It also gets rid of the N6xxx notation in the compatibles and
file names, as they are not really used anymore and often result
in confusion.

This is a breaking change, but the impact shouldn't be too big
and it makes usage and maintenance easier in the future.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

Avoid the following checkpatch warning:

include/dt-bindings/clock/imx8mm-clock.h:284: check: Please don't use
 multiple blank lines
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

The DT nodes of the SPI IP's may contain DMA related properties so
make sure that the binding is able to properly validate those as
well by making it aware of these optional properties.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-5-sergiu.moga@microchip.com

Add the missing required DT property `atmel,usart-mode` to the serial
nodes of Atmel/Microchip DT files.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-4-sergiu.moga@microchip.com

Maintain consistency among the compatibles of the serial nodes of
sam9x60ek and highlight the incremental characteristic of its serial
IP's by making sure that all serial nodes contain both the sam9x60
and sam9260 usart/dbgu compatibles.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-3-sergiu.moga@microchip.com

Swap the rx and tx of the DMA related DT properties of the spi11 node
in order to maintain consistency across Microchip/Atmel SoC files.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220913142205.162399-2-sergiu.moga@microchip.com

This pull request contains Broadcom ARM64-based SoC changes for 6.1,
please pull the following:

- Rafal adds the BCM4908 LED controller node and describes all 32 LED
pins, he also adds support for the Asus GC-AC5300 LEDs

* tag 'arm-soc/for-6.1/devicetree-arm64' of https://github.com/Broadcom/stblinux:
  arm64: dts: broadcom: bcm4908: add Asus GT-AC5300 LEDs
  arm64: dts: broadcom: bcm4908: add LEDs controller block
  arm64: dts: broadcom: bcm4908: add remaining LED pins

Link: https://lore.kernel.org/r/20220915023044.2350782-3-f.fainelli@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

This pull request contains Broadcom ARM-based SoC Device Tree updates
for 6.1, please pull the following:

- Rafal improves the BCM5301X PCIe DT nodes schema validation by
flagging the PCIe controller with a missing "device_type" property

- William merges BCM4908 within BCMBCA since this chip is part of the
Broadcom Broadband Carrier Access group and follows the architecture of
those chips

* tag 'arm-soc/for-6.1/devicetree' of https://github.com/Broadcom/stblinux:
  arm64: bcmbca: Merge ARCH_BCM4908 to ARCH_BCMBCA
  arm64: dts: Add BCM4908 generic board dts
  arm64: dts: Move BCM4908 dts to bcmbca folder
  arm64: dts: bcmbca: update BCM4908 board dts files
  dt-bindings: arm64: bcmbca: Update BCM4908 description
  dt-bindings: arm64: bcmbca: Merge BCM4908 into BCMBCA
  ARM: dts: BCM5301X: Add basic PCI controller properties

Link: https://lore.kernel.org/r/20220915023044.2350782-2-f.fainelli@gmail.comSigned-off-by: Arnd Bergmann <arnd@arndb.de>

Add dma properties to support GPCDMA for I2C in Tegra 186 and later
chips
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add the iommus property to the HDA node on Tegra234.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Enable HDA node for the Jetson AGX Orin platform.
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add Host1x context isolation domains on Tegra234. On Tegra234 we have
two IOMMUs that are connected to Host1x-channel programmed engines,
so we have to include domains for each of them.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.
Signed-off-by: Thierry Reding <treding@nvidia.com>

The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its Wi-Fi functionality. Tested on Pixel C.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>

The Google Pixel C contains a BRCM4354 Wi-Fi + BT module.
Add a DT node for its BT functionality. Tested on Pixel C.
Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
Signed-off-by: Thierry Reding <treding@nvidia.com>

A Multi-Gigabit Ethernet (MGBE) instance drives the primary Ethernet
port on the Jetson AGX Orin Developer Kit. Enable it.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add device tree nodes for the four instances of the Multi-Gigabit
Ethernet (MGBE) IP found on NVIDIA Tegra234 SoCs.
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

There is no need to list the Tegra194-specific compatible for Tegra234
because the backwards-compatibility goes back all the way to Tegra186.
Signed-off-by: Thierry Reding <treding@nvidia.com>

Enable PCIe controller nodes to enable respective PCIe slots on
P3737-0000 board. Following is the ownership of slots by different
PCIe controllers.
Controller-1 : On-board Broadcom WiFi controller
Controller-4 : M.2 Key-M slot
Controller-5 : CEM form-factor x8 slot
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add P2U (PIPE to UPHY) and PCIe controller nodes to device tree.
The Tegra234 SoC contains 10 PCIe controllers and 24 P2U instances
grouped into three different PHY bricks namely High-Speed IO (HSIO-8 P2Us)
NVIDIA High Speed (NVHS-8 P2Us) and Gigabit Ethernet (GBE-8 P2Us)
respectively.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add regulator supplies required for PCIe functionality. The supplies
include 1.8V, 3.3V and 12V.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

Add defines for stream IDs used for Host1x context isolation
on Tegra234. The same stream IDs are used for both NISO0 and
NISO1 SMMUs since Host1x's stream ID protection tables don't
make a distinction between the two.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>