- 29 Dec, 2023 30 commits
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Ovidiu Panait authored
The sg lists are not unmapped in case of timeout errors. Fix this. Fixes: 5a2bb93f ("crypto: sahara - add support for SHA1/256") Fixes: 5de88752 ("crypto: sahara - Add driver for SAHARA2 accelerator.") Signed-off-by:
Ovidiu Panait <ovidiu.panait@windriver.com> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
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Ovidiu Panait authored
Set the reqsize for sha algorithms to sizeof(struct sahara_sha_reqctx), the extra space is not needed. Fixes: 5a2bb93f ("crypto: sahara - add support for SHA1/256") Signed-off-by:
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Ovidiu Panait authored
In case of a zero-length input, exit gracefully from sahara_aes_crypt(). Fixes: 5de88752 ("crypto: sahara - Add driver for SAHARA2 accelerator.") Signed-off-by:
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Vegard Nossum authored
Commit 31865c4c ("crypto: skcipher - Add lskcipher") moved some fields from 'struct skcipher_alg' into SKCIPHER_ALG_COMMON but didn't remove the corresponding kerneldoc members, which results in these warnings when running 'make htmldocs': ./include/crypto/skcipher.h:182: warning: Excess struct member 'min_keysize' description in 'skcipher_alg' ./include/crypto/skcipher.h:182: warning: Excess struct member 'max_keysize' description in 'skcipher_alg' ./include/crypto/skcipher.h:182: warning: Excess struct member 'ivsize' description in 'skcipher_alg' ./include/crypto/skcipher.h:182: warning: Excess struct member 'chunksize' description in 'skcipher_alg' ./include/crypto/skcipher.h:182: warning: Excess struct member 'stat' description in 'skcipher_alg' ./include/crypto/skcipher.h:182: warning: Excess struct member 'base' description in 'skcipher_alg' SKCIPHER_ALG_COMMON already has the documentation for all these fields. Fixes: 31865c4c ("crypto: skcipher - Add lskcipher") Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by:
Vegard Nossum <vegard.nossum@oracle.com> Reviewed-by:
Randy Dunlap <rdunlap@infradead.org> Tested-by:
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Vegard Nossum authored
Commit 42808e5d ("crypto: hash - Count error stats differently") moved some fields from 'struct shash_alg' into HASH_ALG_COMMON but didn't remove the corresponding kerneldoc members, which results in these warnings when running 'make htmldocs': ./include/crypto/hash.h:248: warning: Excess struct member 'digestsize' description in 'shash_alg' ./include/crypto/hash.h:248: warning: Excess struct member 'statesize' description in 'shash_alg' ./include/crypto/hash.h:248: warning: Excess struct member 'stat' description in 'shash_alg' ./include/crypto/hash.h:248: warning: Excess struct member 'base' description in 'shash_alg' HASH_ALG_COMMON already has the documentation for all these fields. Fixes: 42808e5d ("crypto: hash - Count error stats differently") Cc: Randy Dunlap <rdunlap@infradead.org> Cc: Jonathan Corbet <corbet@lwn.net> Signed-off-by:
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Damian Muszynski authored
The thread-to-arbiter mapping describes which arbiter can assign jobs to an acceleration engine thread. The existing mappings are functionally correct, but hardcoded and not optimized. Replace the static mappings with an algorithm that generates optimal mappings, based on the loaded configuration. The logic has been made common so that it can be shared between all QAT GEN4 devices. Signed-off-by:
Damian Muszynski <damian.muszynski@intel.com> Reviewed-by:
Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by:
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Lucas Segarra Fernandez authored
Expose through debugfs ring pair telemetry data for QAT GEN4 devices. This allows to gather metrics about the PCIe channel and device TLB for a selected ring pair. It is possible to monitor maximum 4 ring pairs at the time per device. For details, refer to debugfs-driver-qat_telemetry in Documentation/ABI. This patch is based on earlier work done by Wojciech Ziemba. Signed-off-by:
Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com> Reviewed-by:
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Lucas Segarra Fernandez authored
Expose through debugfs device telemetry data for QAT GEN4 devices. This allows to gather metrics about the performance and the utilization of a device. In particular, statistics on (1) the utilization of the PCIe channel, (2) address translation, when SVA is enabled and (3) the internal engines for crypto and data compression. If telemetry is supported by the firmware, the driver allocates a DMA region and a circular buffer. When telemetry is enabled, through the `control` attribute in debugfs, the driver sends to the firmware, via the admin interface, the `TL_START` command. This triggers the device to periodically gather telemetry data from hardware registers and write it into the DMA memory region. The device writes into the shared region every second. The driver, every 500ms, snapshots the DMA shared region into the circular buffer. This is then used to compute basic metric (min/max/average) on each counter, every time the `device_data` attribute is queried. Telemetry counters are exposed through debugfs in the folder /sys/kernel/debug/qat_<device>_<BDF>/telemetry. For details, refer to debugfs-driver-qat_telemetry in Documentation/ABI. This patch is based on earlier work done by Wojciech Ziemba. Signed-off-by:
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Lucas Segarra Fernandez authored
Extend the admin interface with two new public APIs to enable and disable the telemetry feature: adf_send_admin_tl_start() and adf_send_admin_tl_stop(). The first, sends to the firmware, through the ICP_QAT_FW_TL_START message, the IO address where the firmware will write telemetry metrics and a list of ring pairs (maximum 4) to be monitored. It returns the number of accelerators of each type supported by this hardware. After this message is sent, the firmware starts periodically reporting telemetry data using by writing into the dma buffer specified as input. The second, sends the admin message ICP_QAT_FW_TL_STOP which stops the reporting of telemetry data. This patch is based on earlier work done by Wojciech Ziemba. Signed-off-by:
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Lucas Segarra Fernandez authored
GET_DEV() macro expansion relies on struct pci_dev being defined. Include <linux/pci.h> at adf_accel_devices.h. Signed-off-by:
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Jiapeng Chong authored
No functional modification involved. ./drivers/crypto/intel/iaa/iaa_crypto_main.c:979:2-3: Unneeded semicolon. Reported-by:
Abaci Robot <abaci@linux.alibaba.com> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7772Signed-off-by:
Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by:
Tom Zanussi <tom.zanussi@linux.intel.com> Signed-off-by:
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Tom Zanussi authored
Remove a stray newline in update_max_adecomp_delay_ns(). Reported-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
Dave Jiang <dave.jiang@intel.com> Reviewed-by:
Fenghua Yu <fenghua.yu@intel.com> Signed-off-by:
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Tom Zanussi authored
In order for shared workqeues to work properly, desc->priv should be set to 0 rather than 1. The need for this is described in commit f5ccf55e (dmaengine/idxd: Re-enable kernel workqueue under DMA API), so we need to make IAA consistent with IOMMU settings, otherwise we get: [ 141.948389] IOMMU: dmar15: Page request in Privilege Mode [ 141.948394] dmar15: Invalid page request: 2000026a100101 ffffb167 Dedicated workqueues ignore this field and are unaffected. Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
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Ovidiu Panait authored
The value of reqsize must only be changed through the helper. Signed-off-by:
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WangJinchao authored
Create a script for comparing tcrypt speed test logs. The script will systematically analyze differences item by item and provide a summary (average). This tool is useful for evaluating the stability of cryptographic module algorithms and assisting with performance optimization. Please note that for such a comparison, stability depends on whether we allow frequency to float or pin the frequency. The script produces comparisons in two scenes: 1. For operations in seconds ================================================================================ rfc4106(gcm(aes)) (pcrypt(rfc4106(gcm_base(ctr(aes-generic),ghash-generic)))) encryption -------------------------------------------------------------------------------- bit key | byte blocks | base ops | new ops | differ(%) 160 | 16 | 66439 | 63063 | -5.08 160 | 64 | 62220 | 57439 | -7.68 ... 288 | 4096 | 15059 | 16278 | 8.09 288 | 8192 | 9043 | 9526 | 5.34 -------------------------------------------------------------------------------- average differ(%s) | total_differ(%) -------------------------------------------------------------------------------- 5.70 | -4.49 ================================================================================ 2. For avg cycles of operation ================================================================================ rfc4106(gcm(aes)) (pcrypt(rfc4106(gcm_base(ctr(aes-generic),ghash-generic)))) encryption -------------------------------------------------------------------------------- bit key | byte blocks | base cycles | new cycles | differ(%) 160 | 16 | 32500 | 35847 | 10.3 160 | 64 | 33175 | 45808 | 38.08 ... 288 | 4096 | 131369 | 132132 | 0.58 288 | 8192 | 229503 | 234581 | 2.21 -------------------------------------------------------------------------------- average differ(%s) | total_differ(%) -------------------------------------------------------------------------------- 8.41 | -6.70 ================================================================================ Signed-off-by:WangJinchao <wangjinchao@xfusion.com> Signed-off-by:
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Nithin Dabilpuram authored
Provide an option in Inline IPsec configure mailbox to configure the CPT_AF_LFX_CTL:CTX_ILEN for inline CPT LF attached to CPT RVU PF. This is needed to set the ctx ilen to size of inbound SA for HW errata IPBUCPT-38756. Not setting this would lead to new context's not being fetched. Also set FLR_FLUSH in CPT_LF_CTX_CTL for CPT LF's as workaround for same errata. Signed-off-by:
Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by:
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Nithin Dabilpuram authored
Register errors interrupts for inline cptlf attached to PF driver so that SMMU faults and other errors can be reported. Signed-off-by:
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Srujana Challa authored
HW has a errata that CPT HW may hit an issue, while processing CPT instructions with CTX_VAL set and CTX_VAL not set. So, this patch adds the code to always set the CTX_VAL as a workaround. Signed-off-by:
Srujana Challa <schalla@marvell.com> Signed-off-by:
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Srujana Challa authored
Updates CPT inbound inline IPsec configure mailbox to take CPT credit threshold and bpid, which are introduced in CN10KB. Signed-off-by:
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Srujana Challa authored
CPT LF must be reset and follow CPT LF disable sequence suggested by HW team, when driver exits. This patch adds code for the same. Signed-off-by:
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Srujana Challa authored
Adds code to not execute CPT errata "when CPT_AF_DIAG[FLT_DIS] = 0 and a CPT engine access to LLC/DRAM encounters a fault/poison, a rare case may result in unpredictable data being delivered to a CPT engine" workaround on CN10KA B0/CN10KB HW as it is fixed on these chips. Signed-off-by:
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Srujana Challa authored
On CN10KA B0/CN10KB, CPT scatter gather format has modified to support multi-seg in inline IPsec. Due to this CPT requires new firmware and doesn't work with CN10KA0/A1 firmware. To make HW works in backward compatibility mode or works with CN10KA0/A1 firmware, a bit(T106_MODE) is introduced in HW CSR. This patch adds devlink parameter for configuring T106_MODE. This patch also documents the devlink parameter under Documentation/crypto/device_drivers. Signed-off-by:
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Srujana Challa authored
Scatter Gather input format for CPT has changed on CN10KB/CN10KA B0 HW to make it compatible with NIX Scatter Gather format to support SG mode for inline IPsec. This patch modifies the code to make the driver works for the same. This patch also enables CPT firmware load for these chips. Signed-off-by:
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Srujana Challa authored
CPT block reset in CPT PF erase all the CPT configuration which is done in AF driver init. So, remove CPT block reset from CPT PF as it is also being done in AF init and not required in PF. Signed-off-by:
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- 22 Dec, 2023 10 commits
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Herbert Xu authored
When ecb is used to wrap an lskcipher, the statesize isn't set correctly. Fix this by making the simple instance creator set the statesize. Reported-by: syzbot+8ffb0839a24e9c6bfa76@syzkaller.appspotmail.com Reported-by:
Edward Adam Davis <eadavis@qq.com> Fixes: 662ea18d ("crypto: skcipher - Make use of internal state") Signed-off-by:
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Thomas Bourgoin authored
smatch warnings: drivers/crypto/stm32/stm32-crc32.c:108 stm32_crc_get_next_crc() warn: can 'crc' even be NULL? Use list_first_entry_or_null instead of list_first_entry to retrieve the first device registered. The function list_first_entry always return a non NULL pointer even if the list is empty. Hence checking if the pointer returned is NULL does not tell if the list is empty or not. Reported-by:
kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/r/202311281111.ou2oUL2i-lkp@intel.com/Reported-by:
Dan Carpenter <error27@gmail.com> Closes: https://lore.kernel.org/r/202311281111.ou2oUL2i-lkp@intel.com/Signed-off-by:
Thomas Bourgoin <thomas.bourgoin@foss.st.com> Signed-off-by:
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Jie Wang authored
Add support for 420xx devices by including a new device driver that supports such devices, updates to the firmware loader and capabilities. Compared to 4xxx devices, 420xx devices have more acceleration engines (16 service engines and 1 admin) and support the wireless cipher algorithms ZUC and Snow 3G. Signed-off-by:
Jie Wang <jie.wang@intel.com> Co-developed-by:
Dong Xie <dong.xie@intel.com> Signed-off-by:
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Jie Wang authored
Relocate the structures adf_fw_objs and adf_fw_config from the file adf_4xxx_hw_data.c to the newly created adf_fw_config.h. These structures will be used by new device drivers. This does not introduce any functional change. Signed-off-by:
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Jie Wang authored
Move logic that is common between QAT GEN4 accelerators to the qat_common folder. This includes addresses of CSRs, setters and configuration logic. When moved, functions and defines have been renamed from 4XXX to GEN4. Code specific to the device is moved to the file adf_gen4_hw_data.c. Code related to configuration is moved to the newly created adf_gen4_config.c. This does not introduce any functional change. Signed-off-by:
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Jie Wang authored
Add accel_dev as parameter of the function uof_get_num_objs(). This is in preparation for the introduction of the QAT 420xx driver as it will allow to reconfigure the ae_mask when a configuration that does not require all AEs is loaded on the device. This does not introduce any functional change. Signed-off-by:
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Jie Wang authored
Move the function get_service_enabled() from adf_4xxx_hw_data.c to adf_cfg_services.c and rename it as adf_get_service_enabled(). This function is not specific to the 4xxx and will be used by other QAT drivers. This does not introduce any functional change. Signed-off-by:
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Om Prakash Singh authored
Document the crypto engine on the SM7280 Platform. Signed-off-by:
Om Prakash Singh <quic_omprsing@quicinc.com> Reviewed-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by:
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Tianjia Zhang authored
When the mpi_ec_ctx structure is initialized, some fields are not cleared, causing a crash when referencing the field when the structure was released. Initially, this issue was ignored because memory for mpi_ec_ctx is allocated with the __GFP_ZERO flag. For example, this error will be triggered when calculating the Za value for SM2 separately. Fixes: d58bb7e5 ("lib/mpi: Introduce ec implementation to MPI library") Cc: stable@vger.kernel.org # v6.5 Signed-off-by:
Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by:
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Krzysztof Kozlowski authored
All devices compatible with SM8150 QCE (so SM8250 and newer) do not have clock inputs (clocks are handled by secure firmware), so explicitly disallow the clocks in the bindings. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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