- 27 Sep, 2010 1 commit
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Will Deacon authored
The PL310 on the ct-ca9x4 tile for the Versatile Express does not need to add additional latency when accessing its cache RAMs. Unfortunately, the boot monitor sets this up for an 8-cycle delay on reads and writes, resulting in greatly reduced memory performance when the L2 cache is enabled. This patch sets the L2 RAM latencies to the correct value of 1 cycle on the ct-ca9x4 tile before enabling the L2 cache. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 25 Sep, 2010 10 commits
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Santosh Shilimkar authored
On Davinci SRAM is mapped as MT_DEVICE becasue of the section mapping pre-requisite instead of intended MT_MEMORY_NONCACHED Since the section mapping limitation gets fixed with first patch in this series, the MT_MEMORY_NONCACHED can be used now. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Santosh Shilimkar authored
Currently we map 1 MB section while setting up SRAM on OMAPs Regardless of the actual memory. The physical OCM RAM available on OMAP SOCs is in order of KBs. This patch maps only available sram and cleans up some un-necessary cpu_is_xxx checks. Mapping un-available or non-accessible(secure) memory on the newer ARM processor is dangerous. Because ARM CPUs can now speculatively prefetch, we should avoid mapping any no-existing or secure memory. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Santosh Shilimkar authored
This patch populates the L1 entries for MT_MEMORY and MT_MEMORY_NONCACHED types so that at boot-up, we can map memories outside system memory at page level granularity Previously the mapping was limiting to section level, which creates unnecessary additional mapping for which physical memory may not present. On the newer ARM with speculation, this is dangerous and can result in untraceable aborts. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Joe Perches authored
Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Haojian Zhuang authored
While fb isn't active, we should clear CFG_GRA_ENA bit. The existing code can't clear this bit. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Eric Miao authored
When CONFIG_PXA3xx is not selected, cpu_is_pxa3xx() doesn't expand to zero, which in some places doesn't result in correct optimization. Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Reported-and-tested-by: Marek Vasut <marek.vasut@gmail.com>
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Mark F. Brown authored
Reset vector for pxa168 is 0xffff_0000 not 0x0. This fix allows reboot to work Signed-off-by: Mark F. Brown <mark.brown314@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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Marek Vasut authored
Original idea by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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Marek Vasut authored
GPIO 0 is valid, yet this platform doesn't have any power GPIO for MMC. Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
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- 23 Sep, 2010 3 commits
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Nicolas Pitre authored
When the policy for user space is to ignore misaligned accesses from user space, the processor then performs a documented rotation on the accessed data. This is the result of the access being trapped, and the kernel disabling the alignment trap before returning to user space again. In kernel space we always want misaligned accesses to be fixed up. This is enforced by always re-enabling the alignment trap on every entry into kernel space from user space. No such re-enabling is performed when an exception occurs while already in kernel space as the alignment trap is always supposed to be enabled in that case. There is however a small race window when a misaligned access in user space is trapped and the alignment trap disabled, but the CPU didn't return to user space just yet. Any exception would be entered from kernel space at that point and the kernel would then execute with the alignment trap disabled. Thanks to Maxime Bizon <mbizon@freebox.fr> for providing a test module that made this issue reproducible. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Peter Korsgaard authored
Use a correct udelay value to get bus speed around 100KHz. The udelay value was most likely copied from the older devices, but the 9g45 is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a bus speed of around 190KHz, which is too fast for some devices. A udelay value of 5 gives a bus speed of around 90KHz here. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 20 Sep, 2010 4 commits
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Simon Guinot authored
This patch replace all the lock functions with the irq safe variant. The ns2_led_{set,get}_mode() functions must be safe in all context. For example, the trigger timer call led_set_brightness() in a softirq context. Signed-off-by: Simon Guinot <sguinot@lacie.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Eric Miao authored
Signed-off-by: Eric Miao <eric.miao@canonical.com> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Simon Guinot authored
When using simultaneously the two DMA channels on a same engine, some transfers are never completed. For example, an endless lock can occur while writing heavily on a RAID5 array (with async-tx offload support enabled). Note that this issue can also be reproduced by using the DMA test client. On a same engine, the interrupt cause register is shared between two DMA channels. This patch make sure that the cause bit is only cleared for the requested channel. Signed-off-by: Simon Guinot <sguinot@lacie.com> Tested-by: Luc Saillard <luc@saillard.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
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Arnaud Patard authored
The support for the 2 pcie port of the 6282 has broken i/o port by switching *_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same bug solved by commit 35f029e2. So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is working again. Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org> Acked-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net> Cc: stable@kernel.org
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- 19 Sep, 2010 3 commits
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Russell King authored
Jonathan Cameron reports that when using the environment variable KCONFIG_CONFIG, he encounters this error: make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds' Reported-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Catalin Marinas authored
ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Peter Korsgaard authored
5cfc8ee0 (ARM: convert arm to arch_gettimeoffset()) marked all of at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high res timer support / accurate clock_gettime() - But only at91x40 needs it. Cc: stable@kernel.org Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> Acked-by: John Stultz <johnstul@us.ibm.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 17 Sep, 2010 9 commits
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Daniel Walker authored
Setting of these bits can cause issues on other SMP SoC's not produced by ARM. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Russell King authored
Al Viro reports that calling "sys_sigsuspend(-ERESTARTNOHAND, 0, 0)" with two signals coming and being handled in kernel space results in the syscall restart being done twice. Avoid this by clearing the 'why' flag when we call the signal handling code to prevent further syscall restarts after the first. Acked-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Catalin Marinas authored
Clearing bit 22 in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. Cc: Nicolas Pitre <nicolas.pitre@linaro.org> Cc: <stable@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Will Deacon authored
On the r2p0, r2p1 and r2p2 versions of the Cortex-A9, data corruption can occur if a shared cache line is replaced on one CPU as another CPU is accessing it. This workaround sets two bits in the diagnostic register of the Cortex-A9, reducing the linefill issuing capabilities of the processor and avoiding the erroneous behaviour. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Will Deacon authored
On versions of the Cortex-A9 up to and including r2p2, under rare circumstances, a DMB instruction between 2 write operations may not ensure the correct visibility ordering of the 2 writes. This workaround sets a bit in the diagnostic register of the Cortex-A9, causing the DMB instruction to behave like a DSB, which functions correctly on the affected cores. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Will Deacon authored
Kconfig doesn't have any knowledge of specific v7 cores, so it is possible to select errata workarounds that may cause inadvertent behaviour when executed on a core other than those targetted by the fix. This patch improves the variant and revision checking in proc-v7.S so that the primary part number is also considered when applying errata workarounds. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Linus Walleij authored
We have to use _cansleep gpio accessors in the MMCI driver so as to avoid slowpath warnings, now U300 has MMCI but doesn't have these functions in place to siply wrap the existing non-sleeping functions into sleepable variants. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Linus Walleij authored
The prescaler 16 is now used only when the timer runs at 32 MHz or more. Some comment updates as well. Acked-by: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Linus Walleij authored
timer0 to 3 are all on mtu block 0, so don't calculate the clock event rate based upon mtu block 1's clock speed. Acked-by: Alessandro Rubini <rubini@unipv.it> Signed-off-by: Jonas Aaberg <jonas.aberg@stericsson.com> Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- 16 Sep, 2010 10 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6Linus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6: cifs: fix potential double put of TCP session reference
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git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6Linus Torvalds authored
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6: [IA64] Optimize ticket spinlocks in fsys_rt_sigprocmask
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git://github.com/schandinat/linux-2.6Linus Torvalds authored
* '2.6.36-fixes' of git://github.com/schandinat/linux-2.6: drivers/video/via/ioctl.c: prevent reading uninitialized stack memory
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git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6Linus Torvalds authored
* 'urgent' of git://git.kernel.org/pub/scm/linux/kernel/git/brodo/pcmcia-2.6: pcmcia pcnet_cs: try setting io_lines to 16 if card setup fails pcmcia: per-device, not per-socket debug messages pcmcia serial_cs.c: fix multifunction card handling
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git://git.infradead.org/users/cbou/battery-2.6.36Linus Torvalds authored
* git://git.infradead.org/users/cbou/battery-2.6.36: apm_power: Add missing break statement intel_pmic_battery: Fix battery charging status on mrst
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git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdogLinus Torvalds authored
* git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog: watchdog: Enable NXP LPC32XX support in Kconfig (resend) watchdog: ts72xx_wdt: disable watchdog at probe watchdog: sb_wdog: release irq and reboot notifier in error path and module_exit()
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git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tileLinus Torvalds authored
* 'stable' of git://git.kernel.org/pub/scm/linux/kernel/git/cmetcalf/linux-tile: arch/tile: fix formatting bug in register dumps arch/tile: fix memcpy_fromio()/memcpy_toio() signatures arch/tile: Save and restore extra user state for tilegx arch/tile: Change struct sigcontext to be more useful arch/tile: finish const-ifying sys_execve()
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git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6Linus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/lrg/voltage-2.6: regulator: wm8350-regulator - fix the logic of checking REGULATOR_MODE_STANDBY mode regulator: wm831x-ldo - fix the logic to set REGULATOR_MODE_IDLE and REGULATOR_MODE_STANDBY modes regulator: ab8500 - fix off-by-one value range checking for selector regulator: 88pm8607 - fix value range checking for accessing info->vol_table regulator: isl6271a-regulator - fix regulator_desc parameter for regulator_register() regulator: ad5398 - fix a memory leak regulator: Update e-mail address for Liam Girdwood regulator: set max8998->dev to &pdev->dev. regulator: tps6586x-regulator - fix bit_mask parameter for tps6586x_set_bits() regulator: tps6586x-regulator - fix value range checking for val regulator: max8998 - set max8998->num_regulators regulator: max8998 - fix memory allocation size for max8998->rdev regulator: tps6507x - remove incorrect comments regulator: max1586 - improve the logic of choosing selector regulator: ab8500 - fix the logic to remove already registered regulators in error path regulator: ab3100 - fix the logic to remove already registered regulators in error path regulator/ab8500: move dereference below the check for NULL
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git://git.kernel.org/pub/scm/linux/kernel/git/tj/wqLinus Torvalds authored
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq: workqueue: add documentation
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git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6Linus Torvalds authored
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: only warn on mipmap size checks in r600 cs checker (v2) drm/radeon/kms: force legacy pll algo for RV620 LVDS drm: fix race between driver loading and userspace open. drm: Use a nondestructive mode for output detect when polling (v2) drm/radeon/kms: fix the colorbuffer CS checker for r300-r500 drm/radeon/kms: increase lockup detection interval to 10 sec for r100-r500 drm/radeon/kms/evergreen: fix backend setup drm: Use a nondestructive mode for output detect when polling drm/radeon: add some missing copyright headers drm: Only decouple the old_fb from the crtc is we call mode_set* drm/radeon/kms: don't enable underscan with interlaced modes drm/radeon/kms: add connector table for Mac x800 drm/radeon/kms: fix regression in RMX code (v2) drm: Fix regression in disable polling e58f637b
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