- 09 Oct, 2023 40 commits
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Christian König authored
bo->tbo.resource can easily be NULL here. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2902Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Aric Cyr authored
This version brings along following fixes: - Refactor DPG test pattern logic for ODM cases - Refactor HWSS into component folder - Revert "drm/amd/display: Add a check for idle power optimization" - Revert "drm/amd/display: remove duplicated edp relink to fastboot - Update cursor limits based on SW cursor fallback limits - Update stream mask - Update pmfw_driver_if new structure - Modify SMU message logs - Don't set dpms_off for seamless boot Known issue: DWB (Writeback functionality) is broken. Fix will be available in DC 3.2.256 Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
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Stylon Wang authored
[Why] This could work around the issue with DP tunneling producing a NULL pointer dereference. [How] Disable the virtual links. Reviewed-by:
Stylon Wang <stylon.wang@amd.com> Tested-by:
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George Shen authored
[Why] Enabling DPG causes HUBP to stay in blank constantly. If DPG is enabled while an MCLK switch is taking place with SubVP, it will cause the MCLK to never complete. This is because SubVP MCLK switch relies a HUBP VLine interrupt, which will never occur when HUBP is constantly in blank. [How] Disable SubVP when test pattern is enabled. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Nevenko Stupar <nevenko.stupar@amd.com> Acked-by:
George Shen <george.shen@amd.com> Tested-by:
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George Shen authored
[Why] Current DPG test pattern logic does not account for ODM configuration changes after test pattern has already been programmed. For example, if ODM2:1 is enabled after test pattern is already being output, the second pipe is not programmed to output test pattern, causing half the screen to be black. [How] Move DPG test pattern parameter calculations into separate function. Whenever ODM pipe configuration changes, re-calculate DPG test pattern parameters and program DPG if test pattern is currently enabled. Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
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Daniel Miess authored
[Why] eDPs fail to light up with seamless boot enabled [How] When seamless boot is enabled don't configure dpms_off in disable_vbios_mode_if_required. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Acked-by:
Daniel Miess <daniel.miess@amd.com> Tested-by:
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Mounika Adhuri authored
[why] Rename hw_sequencer to hwseq. Move all hwseq files to unique folder hwss. [how] creating hwss repo in dc, and moved the dcnxx_hwseq.c and .h files into corresponding new folders inside the hwss and cleared the linkage errors by adding relative paths in the Makefile.template. Reviewed-by:
Martin Leung <martin.leung@amd.com> Acked-by:
Mounika Adhuri <moadhuri@amd.com> Tested-by:
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Sung Joon Kim authored
Revert commit 434cf7af ("drm/amd/display: Add a check for idle power optimization") Because it cause Freesync and S4 regression Reviewed-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Yifan Zhang authored
add hub->ctx_distance when read CONTEXT1_CNTL, align w/ write back operation. v2: fix coding style errors reported by checkpatch.pl (Christian) Signed-off-by:
Yifan Zhang <yifan1.zhang@amd.com> Acked-by:
Lang Yu <lang.yu@amd.com> Signed-off-by:
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Nicholas Kazlauskas authored
[Why] These functions can be called from high IRQ levels and the OS will hang if it tries to use a usleep_highres or a msleep. [How] Replace the fsleep with a udelay. Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by:
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Alvin Lee authored
[Why&How] For determining the cursor size limit, use the same checks that are used for determining SW cursor fallback instead of only using SubVP Reviewed-by:
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Muhammad Ahmed authored
[why] Need to use real clock table [How] Update the clock table Reviewed-by:
Muhammad Ahmed <ahmed.ahmed@amd.com> Tested-by:
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Duncan Ma authored
[Why] Whenever stream changes because of new pipe arrangements such as ODM. The new stream mask is not reflected in DMCUB. The mismatch in stream mask is blocking ips entry in some scenarios. [How] Whenever stream arrangement changes, update stream mask and notify DMCUB. Reviewed-by:
Duncan Ma <duncan.ma@amd.com> Tested-by:
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Aric Cyr authored
Revert commit 984abb53 ("drm/amd/display: remove duplicated edp relink to fastboot") Because it cause 4k EDP not light up on boot Reviewed-by:
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Max Tseng authored
Fine tune the Vmin clock value Reviewed-by:
Robin Chen <robin.chen@amd.com> Acked-by:
Max Tseng <max.tseng@amd.com> Tested-by:
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Charlene Liu authored
[why] pmfw header file updated, need align with data structure. [How] Update the data structure. Reviewed-by:
Sung joon Kim <sungjoon.kim@amd.com> Acked-by:
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Muhammad Ansari authored
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Muhammad Ansari <muhammad.ansari@amd.com> Tested-by:
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Sung Joon Kim authored
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by:
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Stanley.Yang authored
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yifan Zhang authored
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by:
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Lijo Lazar authored
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by:
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Lijo Lazar authored
Keep FRU related information together in a separate structure. Signed-off-by:
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Yang Wang authored
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Boyuan Zhang authored
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
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Gabe Teeger authored
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Daniel Miess authored
Update DML2 with replay vblank logic found in DML1. Reviewed-by:
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Saaem Rizvi authored
[Why] There are certain cases during a transition to ODM that might cause corruption on the display. This occurs when we choose certain pipes in a particular state. [How] We now will store the pipe indexes of the any pipes that might be problematic to switch to during an ODM transition, and only use them as a last resort. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Signed-off-by:
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Charlene Liu authored
dc->dml2_options.use_native_pstate_optimization flag will make driver use dcn32 legacy_svp_drr related tuning. Set this to false fixed the stutter underflow issue also based on HW suggest disable ODM by default and let DML choose it. Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Acked-by:
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Sung Joon Kim authored
[why] Surface height/width for Chroma has another variable that it should be intialized to, chroma_size. Fixing this will help pass DML2.0 validation for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012. [how] Assign SurfaceHeight/WidthC to chroma_size.height/width Reviewed-by:
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Taimur Hassan authored
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by:
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Sung Joon Kim authored
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by:
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Sung Joon Kim authored
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by:
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Charlene Liu authored
Add z8 watermarks to struct for later ASIC use. Reviewed-by:
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Qingqing Zhuo authored
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Qingqing Zhuo authored
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by:
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Rodrigo Siqueira authored
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by:
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Rodrigo Siqueira authored
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by:
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