- 15 Jan, 2021 4 commits
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Ville Syrjälä authored
Let's not enable the 4:4:4->4:2:0 conversion bit in the DFP unless we're actually outputting YCbCr 4:4:4. It would appear some protocol converters blindy consult this bit even when the source is outputting RGB, resulting in a visual mess. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2914Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210111164111.13302-1-ville.syrjala@linux.intel.com Fixes: 181567aa ("drm/i915: Do YCbCr 444->420 conversion via DP protocol converters") Reviewed-by:
Jani Nikula <jani.nikula@intel.com>
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Lyude Paul authored
In the next commit where we split PWM related backlight functions from higher-level backlight functions, we'll want to be able to retrieve the backlight level for the current display panel from the intel_panel_bl_funcs->setup() function using pwm_funcs->get(). Since intel_panel_bl_funcs->setup() is called before we've fully read in the current hardware state into our atomic state, we can't grab atomic modesetting locks safely anyway in intel_panel_bl_funcs->setup(), and some PWM backlight functions (vlv_get_backlight() in particular) require knowing the currently used pipe we need to be able to discern the current display pipe through other means. Luckily, we're already passing the current display pipe to intel_panel_bl_funcs->setup() so all we have to do in order to achieve this is pass down that parameter to intel_panel_bl_funcs->get(). So, fix this by accepting an additional pipe parameter in intel_panel_bl_funcs->get(), and leave figuring out the current display pipe up to the caller. Signed-off-by:
Lyude Paul <lyude@redhat.com> Signed-off-by:
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Zhenyu Wang authored
Some vmm like hyperv and crosvm don't supply any ISA bridge to their guest, when igd passthrough is equipped on these vmm, guest i915 display may couldn't work as guest i915 detects PCH_NONE pch type. When i915 runs as guest, this patch guess pch type through gpu type even without ISA bridge. v2: Fix CI warning v3: Add HAS_DISPLAY()= true condition beforce guessing virt pch, then refactori. v4: Fix CI warning Signed-off-by:Zhenyu Wang <zhenyuw@linux.intel.com> Co-developed-by:
Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by:
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Chris Wilson authored
drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should this be a bitwise op? drivers/gpu/drm/i915/display/intel_dp.c:6922 intel_dp_update_420() warn: should this be a bitwise op? drivers/gpu/drm/i915/display/intel_dp.c:6923 intel_dp_update_420() warn: should this be a bitwise op? Inside drm_dp_downstream_rgb_to_ycbcr_conversion(), that parameter 'color_spc' is used as return port_cap[3] & color_spc, implying that it is indeed a mask and not a boolean value. Fixes: 522508b6 ("drm/i915/display: Let PCON convert from RGB to YCbCr if it can") Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ankit Nautiyal <ankit.k.nautiyal@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Reviewed-by:
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- 14 Jan, 2021 17 commits
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Ville Syrjälä authored
We dropped the other redundant master_transcoder assignments earlier, but this one slipped through. Get rid of it as well. The crtc state gets fully reset before readout so there is no point in doing this. Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com>
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José Roberto de Souza authored
DG1 is missing those two WA so instead of copy and paste it to the DG1 function, here calling the function that implements it. While at it also renaming tgl_init_clock_gating to gen12lp_init_clock_gating as it is also used by DG1, RKL and ADL-S. Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210113133759.72055-1-jose.souza@intel.com
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Jani Nikula authored
There are a number of functions that "init" pps in various ways. Try to find some more consistency in the naming. Rename: - intel_dp_init_panel_power_sequencer -> pps_init_delays - intel_dp_init_panel_power_sequencer_registers -> pps_init_registers - intel_dp_init_panel_power_timestamps -> pps_init_timestamps as this is what the functions do. Skip the intel_ prefix here to emphasize these are static and not exported. No functional changes. Reviewed-by:
Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by:
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Jani Nikula authored
This function is a bit of an outlier, but try to change to a name that is more in line with the rest of the intel_pps functions. No functional changes. Reviewed-by:
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Jani Nikula authored
Prefer keeping the unlocked variants hidden if possible. No functional changes. Reviewed-by:
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Jani Nikula authored
Follow the usual naming pattern for functions. "reset all" because it iterates over all DP encoders. No functional changes. Reviewed-by:
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Jani Nikula authored
Follow the usual naming pattern for functions. No functional changes. Reviewed-by:
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Jani Nikula authored
Add an "encoder reset" call to hide some more pps functions, and clean up the callers. A minor functional change is not holding the pps lock across the whole operation in intel_dp_encoder_reset, but instead doing it in two steps. v2: rename intel_pps_reinit to intel_pps_encoder_reset for clarity Reviewed-by:
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Jani Nikula authored
Add a new init call to be called only once, unlike some of the other various init calls. This lets us hide more functions within intel_pps.c. No functional changes. Reviewed-by:
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Jani Nikula authored
Add a locked version of intel_pps_vdd_off_sync_unlocked() that does everything the callers expect it to. No functional changes. v2: Fix typo (Anshuman) Reviewed-by:
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Jani Nikula authored
Follow the usual naming pattern for functions, both for the prefix and the _unlocked suffix for functions that expect the lock to be held when calling. No functional changes. Reviewed-by:
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Jani Nikula authored
Follow the usual naming pattern for functions. We don't need to repeat "panel" here. No functional changes. v2: Fix comment (Anshuman) Reviewed-by:
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Jani Nikula authored
Follow the usual naming pattern for functions. No functional changes. Reviewed-by:
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Jani Nikula authored
Start following the usual naming pattern for functions. No functional changes. Reviewed-by:
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Jani Nikula authored
In a long overdue refactoring, split out all panel sequencer code from intel_dp.c to new intel_pps.[ch]. The first part is mostly just code movement as-is, without cleanups or functional changes. We need to add a vlv_get_dpll() helper to get at the vlv/chv dpll from pps code. v2: Rebase. Reviewed-by:
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Jani Nikula authored
Always prefer the kernel types over stdint types in i915. Cc: Imre Deak <imre.deak@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
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Jani Nikula authored
skl_scaler_get_filter_select() isn't static and can't be inline. Reviewed-by:
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- 13 Jan, 2021 19 commits
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Imre Deak authored
The DP PHY vswing/pre-emphasis level programming the driver does is related to the DPTX -> first LTTPR link segment only. Accordingly it should be only programmed when link training the first LTTPR and kept as-is when training subsequent LTTPRs and the DPRX. For these latter PHYs the vs/pe levels will be set in response to writing the DP_TRAINING_LANEx_SET_PHY_REPEATERy DPCD registers (by an upstream LTTPR TX PHY snooping this write access of its downstream LTTPR/DPRX RX PHY). The above is also described in DP Standard v2.0 under 3.6.6.1. While at it simplify and add the LTTPR that is link trained to the debug message in intel_dp_set_signal_levels(). Fixes: b30edfd8 ("drm/i915: Switch to LTTPR non-transparent mode link training") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
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Imre Deak authored
intel_dp_set_signal_levels() is needed for link training, so move it to intel_dp_link_training.c. Signed-off-by:
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Anshuman Gupta authored
Enable HDCP 2.2 MST support till Gen12. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Ramalingam C <ramalingam.c@intel.com> Tested-by:
Karthik B S <karthik.b.s@intel.com> Signed-off-by:
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Anshuman Gupta authored
Authenticate and enable port encryption only once for an active HDCP 2.2 session, once port is authenticated and encrypted enable encryption for each stream that requires encryption on this port. Similarly disable the stream encryption for each encrypted stream, once all encrypted stream encryption is disabled, disable the port HDCP encryption and deauthenticate the port. v2: - Add connector details in drm_err. [Ram] - 's/port_auth/hdcp_auth_status'. [Ram] - Added a debug print for stream enc. v3: - uniformity for connector detail in DMESG. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add support for HDCP 2.2 DP MST shim callback. This adds existing DP HDCP shim callback for Link Authentication and Encryption and HDCP 2.2 stream encryption callback. v2: - Added a WARN_ON() instead of drm_err. [Uma] - Cosmetic changes. [Uma] v3: - 's/port_data/hdcp_port_data' [Ram] - skip redundant link check. [Ram] v4: - use pipe instead of port to access HDCP2_STREAM_STATUS Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS and HDCP2_AUTH_STREAM register in i915_reg header. B.Spec: 21780 B.Spec: 14410 B.Spec: 50573 v2 - Modified naming convention of HDCP2_STREAM_STATUS for pre-gen12 platforms inline with B.Spec. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
This requires for HDCP 2.2 MST check link. As for DP/HDMI shims check_2_2_link retrieves the connector from dig_port, this is not sufficient or DP MST connector, there can be multiple DP MST topology connector associated with same dig_port. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Add support for multiple mst stream in hdcp port data which will be used by RepeaterAuthStreamManage msg and HDCP 2.2 security f/w for m' validation. Security f/w doesn't have any provision to mark the stream_type for each stream separately, it just take single input of stream_type while authenticating the port and applies the same stream_type to all streams. So driver mark each stream_type with common highest supported content type for all streams in DP MST Topology. Security f/w supports RepeaterAuthStreamManage msg and m' validation only once during port authentication and encryption. Though it is not compulsory, security fw should support dynamic update of content_type and should support RepeaterAuthStreamManage msg and m' validation whenever required. v2: - Init the hdcp port data k for HDMI/DP SST stream. v3: - Cosmetic changes. [Uma] v4: - 's/port_auth/hdcp_port_auth'. [Ram] - Commit log improvement. v5: - Comment and commit log improvement. [Ram] v6: - Check first connector connected status before intel_encoder_is_mst to avoid any NULL pointer dereference. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Juston Li <juston.li@intel.com> Acked-by:
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Anshuman Gupta authored
Let's define Maximum MST content streams up to four generically which can be supported by modern display controllers. Cc: Sean Paul <seanpaul@chromium.org> Cc: Ramalingam C <ramalingam.c@intel.com> Acked-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by:
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Anshuman Gupta authored
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size. It is based upon the actual number of MST streams and size of wired_cmd_repeater_auth_stream_req_in. Excluding the size of hdcp_cmd_header. v2: - hdcp_cmd_header size annotation nitpick. [Tomas] Cc: Tomas Winkler <tomas.winkler@intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Acked-by:
Tomas Winkler <tomas.winkler@intel.com> Reviewed-by:
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Anshuman Gupta authored
hdcp_port_data is specific to a port on which HDCP encryption is getting enabled, so encapsulate it to intel_digital_port. This will be required to enable HDCP 2.2 stream encryption. v2: - 's/port_data/hdcp_port_data'. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Pass dig_port as an argument to intel_hdcp_init() and intel_hdcp2_init(). This will be required for HDCP 2.2 stream encryption. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Enable HDCP 1.4 over DP MST for Gen12. v2: - Enable HDCP for <= Gen12 platforms. [Ram] v3: - Connector detials in debug msg. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Enable HDCP 1.4 DP MST stream encryption. Enable stream encryption once encryption is enabled on the DP transport driving the link for each stream which has requested encryption. Disable stream encryption for each stream that no longer requires encryption before disabling HDCP encryption on the link. v2: - Added debug print for stream encryption. - Disable the hdcp on port after disabling last stream encryption. v3: - Cosmetic change, removed the value less comment. [Uma] v4: - Split the Gen12 HDCP enablement patch. [Ram] - Add connector details in drm_err. v5: - uniformity for connector detail in DMESG. [Ram] - comments improvement. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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Anshuman Gupta authored
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP encryption over DP MST Transport Link. HDCP 1.4 stream encryption requires to validate the stream encryption status in HDCP_STATUS_{TRANSCODER,PORT} register driving that link in order to enable/disable the stream encryption. Both of above requirement are same for all Gen with respect to B.Spec Documentation. v2: - Cosmetic changes function name, error msg print and stream typo fixes. [Uma] v3: - uniformity for connector detail in DMESG. [Ram] Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
DP MST stream encryption status requires time of a link frame in order to change its status, but as there were some HDCP encryption timeout observed earlier, it is safer to use ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too, it requires to move the macro to a header. It will be used by both HDCP{1.x,2.x} stream status timeout. Related: 'commit 7e90e8d0 ("drm/i915: Increase timeout for Encrypt status change")' Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine instances lies in Transcoder instead of DDI as in Gen11. This requires hdcp driver to use mst_master_transcoder for link authentication and stream transcoder for stream encryption separately. This will be used for both HDCP 1.4 and HDCP 2.2 over DP MST on Gen12. Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: -
Anshuman Gupta authored
There can be situation when DP MST connector is created without mst modeset being done, in those cases connector->encoder will be NULL. MST connector->encoder initializes after modeset. Don't enable HDCP in such cases to prevent any crash. Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Juston Li <juston.li@intel.com> Tested-by:
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Anshuman Gupta authored
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0 It requires to call intel_hdcp_handle_cp_irq() in case of CP_IRQ is triggered by a sink in DP-MST topology. Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com> Cc: Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
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