- 08 Apr, 2013 25 commits
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Doug Anderson authored
The exynox4210-ehci and exynos4210-ohci nodes need a clock specified using the common clock framework. Document it. Signed-off-by:
Doug Anderson <dianders@chromium.org> Acked-by:
Jingoo Han <jg1.han@samsung.com> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Doug Anderson authored
This is a fixup to two device tree nodes that have already landed but without clock nodes since the transition to common clock happened at the same time. Signed-off-by:
Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by:
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Alexander Graf authored
The exynos 5250 SoC supports A15 style architected timers. Indicate this through the device tree. This is required by KVM. Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Alexander Graf authored
The GIC in the exynos5250 SoC is A15 compliant. Show this through the device tree, so that we can use the GIC for KVM. Also add the respective A15 memory regions and interrupt links. Signed-off-by:
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Sachin Kamat authored
Added HDMI hot plug and regulator nodes to Arndale DT file. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by:
Tushar Behera <tushar.behera@linaro.org> Signed-off-by:
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Sachin Kamat authored
Added MFC codec node to Arndale DT file. Signed-off-by:
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Sachin Kamat authored
Added vmmc regulator node to Arndale DT file. Signed-off-by:
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Amit Daniel Kachhap authored
Added S5M8767 PMIC DT nodes for Arndale board. Only the used LDO's/BUCK are defined here. Also the nodes describe the default/reset state LDO's and no power mangement tuning is implemented. The usage desription can be found in s5m8767 device tree binding documentation. Signed-off-by:
Amit Daniel Kachhap <amit.daniel@samsung.com> Signed-off-by:
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Tushar Behera authored
Added GPIO buttons DT node to Arndale board file. Signed-off-by:
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Sachin Kamat authored
This is required to keep the existing functionality of having no write protect pin on Arndale board. Signed-off-by:
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Tushar Behera authored
Signed-off-by:
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Thomas Abraham authored
Add default pin state information for all client nodes that require pin configuration support using pinctrl interface. Signed-off-by:
Thomas Abraham <thomas.abraham@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Tested-by:
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Thomas Abraham authored
Add default pin state information for all client nodes that require pin configuration support using pinctrl interface. Signed-off-by:
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Sachin Kamat authored
Added documentaion about G2D bindings. Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Inki Dae <inki.dae@samsung.com> Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Origen4412 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to SMDK4412 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to exynos4x12.dtsi file. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Origen4210 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to SMDKV310 board. Signed-off-by:
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Sachin Kamat authored
Added G2D DT node to Exynos4210. Signed-off-by:
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Kukjin Kim authored
Conflicts: arch/arm/boot/dts/exynos4.dtsi arch/arm/boot/dts/exynos5440.dtsi
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Thomas Abraham authored
The functions exynos4_clk_init and exynos4_clk_register_fixed_ext are applicable only on Exynos4 non-dt platforms. But when building Exynos5 platforms without including Exynos4 platforms, the following errors show up. arch/arm/mach-exynos/built-in.o: In function `exynos_init_time': arch/arm/mach-exynos/common.c:446: undefined reference to `exynos4_clk_init' arch/arm/mach-exynos/common.c:447: undefined reference to `exynos4_clk_register_fixed_ext' Fix this compilation errors by marking these calls as Exynos4 specific. Signed-off-by:
Thomas Abraham <thomas.ab@samsung.com> Signed-off-by:
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Tushar Behera authored
In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide) instead of RATIO bit-field (4-bit wide) for dividing clock rate. With current common clock setup, we are using RATIO bit-field which is creating FIFO read errors while accessing eMMC. Changing over to use PRE_RATIO bit-field fixes this issue. dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020) mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0 end_request: I/O error, dev mmcblk0, sector 1 Signed-off-by:Mike Turquette <mturquette@linaro.org> Signed-off-by:
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Sylwester Nawrocki authored
This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1, ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1, DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are available to the consumers (Exynos4x12 FIMC-IS subsystem). While at it, indentation of the mux clocks table is corrected. Signed-off-by:
Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by:
Kyungmin Park <kyungmin.park@samsung.com> Acked-by:
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Sachin Kamat authored
Fixes the below compilation error during non-dt build. drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext': drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration] drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token Signed-off-by:
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- 04 Apr, 2013 15 commits
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Leela Krishna Amudala authored
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi. Register it to common clock framework. Signed-off-by:
Leela Krishna Amudala <l.krishna@samsung.com> Signed-off-by:
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Tomasz Figa authored
This patch extends suspend/resume support for SoC-specific registers to handle differences in register sets on particular SoCs. Signed-off-by:
Tomasz Figa <t.figa@samsung.com> Signed-off-by:
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Tomasz Figa authored
This patch adds missing clock control registers to the list of registers that should be saved across system suspend. Signed-off-by:
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Tomasz Figa authored
This register is present on all Exynos4 SoCs and so the prefix is misleading. Signed-off-by:
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Tomasz Figa authored
This definition is specific for Exynos4210 (which has another location than the same register on Exynos4x12 SoCs) and so needs appropriate prefix. Signed-off-by:
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Tomasz Figa authored
This patch adds E4210 prefix to all registers related to LCD1 clock domain, because they are present only on Exynos4210. Signed-off-by:
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Tomasz Figa authored
Current clock save list is shared for all Exynos4 SoCs, so it must contain only registers present in all supported SoCs, because accessing unavailable registers might have undefined effect. This patch removes registers specific for particular SoCs from shared save list, as they should be supported by separate SoC-specific lists. Signed-off-by:
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Tomasz Figa authored
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers, but they are not used for clock definitions. This patch modifies related clock definitions to use defined macros instead of numeric offsets. Signed-off-by:
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Tomasz Figa authored
This patch adds preprocessor definitions of EPLL and VPLL registers and replaces all occurences of offsets of related registers with new definitions. Signed-off-by:
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Tomasz Figa authored
This patch adds missing mout_sata that is a parent of div_sata clock. Signed-off-by:
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Andrzej Hajda authored
The patch adds missing clocks to TOP and ISP clock domains. It also adds clock gates for ISP sub-blocks. Signed-off-by:
Andrzej Hajda <a.hajda@samsung.com> Signed-off-by:
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Tomasz Figa authored
This patch adds clocks needed for G3D block present on Exynos 4 SoCs. Signed-off-by:
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Sylwester Nawrocki authored
This patch adds several gate and mux clocks related to camera and ISP blocks. Signed-off-by:
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Tomasz Figa authored
This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by:
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Tomasz Figa authored
Unimplemented clock operations should be simply omitted instead of returning error values. This patch removes unimplemented PLL operations to fix problems caused by returning error code in round_rate callback. Signed-off-by:
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