The CONFIG_MIPS_CPS SMP implementation should be able to handle all
cases the CONFIG_MIPS_CMP implementation does, but without requiring
bootloader assistance. It is also required in order to make use of
features such as hotplug & cpuidle core power gating. Enable it by
default for Malta configs that previously enabled the now deprecated
CONFIG_MIPS_CMP, and disable the latter. The local version suffix "cmp"
is removed rather than replaced with "cps" since there are other ways to
tell that the CPS SMP implementation is in use (the "VPE topology" line
in the boot log being one).
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch adds a cpuidle driver for systems based around the MIPS
Coherent Processing System (CPS) architecture. It supports four idle
states:

  - The standard MIPS wait instruction.

  - The non-coherent wait, clock gated & power gated states exposed by
    the recently added pm-cps layer.

The pm-cps layer is used to enter all the deep idle states. Since cores
in the clock or power gated states cannot service interrupts, the
gic_send_ipi_single function is modified to send a power up command for
the appropriate core to the CPC in cases where the target CPU has marked
itself potentially incoherent.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Declaring this allows drivers which need to initialise each struct
cpuidle_device at initialisation time to make use of the structures
already defined in cpuidle.c, rather than having to wastefully define
their own.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch simply includes the cpuidle Kconfig entries in preparation
for cpuidle drivers used on MIPS systems.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Defines a macro intended to allow trivial use of the regular MIPS wait
instruction from cpuidle drivers, which may simply invoke the macro
within their array of states.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Rather than hardcoding CCA=0x5 for secondary cores, re-use the CCA from
the boot CPU. This allows overrides of the CCA using the cca= kernel
parameter to take effect on all CPUs for consistency.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch sets a default CCA suited for use with multi-core SMP on all
current MIPS CPS based systems. It may still be overriden by the cca=
argument on the kernel command line.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

If the user or bootloader sets the CCA to a value which is not suited
for multi-core SMP (ie. anything non-coherent) then limit the system to
using only a single core and warn the user.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch adds support for offlining CPUs via hotplug when using the
CONFIG_MIPS_CPS SMP implementation. When a CPU is offlined one of 2
things will happen:

  - If the CPU is part of a core which implements the MT ASE and there
    is at least one other VPE online within that core then the VPE will
    be halted by settings its TCHalt bit.

  - Otherwise if supported the core will be powered down via the CPC.

  - Otherwise the CPU will hang by executing an infinite loop.

Bringing CPUs back online is then a process of either clearing the
appropriate VPEs TCHalt bit or powering up the appropriate core via the
CPC. Throughout the process the struct core_boot_config vpe_mask field
must be maintained such that mips_cps_boot_vpes will start & stop the
correct VPEs.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch adds code to generate entry & exit code for various low power
states available on systems based around the MIPS Coherent Processing
System architecture (ie. those with a Coherence Manager, Global
Interrupt Controller & for >=CM2 a Cluster Power Controller). States
supported are:

  - Non-coherent wait. This state first leaves the coherent domain and
    then executes a regular MIPS wait instruction. Power savings are
    found from the elimination of coherency interventions between the
    core and any other coherent requestors in the system.

  - Clock gated. This state leaves the coherent domain and then gates
    the clock input to the core. This removes all dynamic power from the
    core but leaves the core at the mercy of another to restart its
    clock. Register state is preserved, but the core can not service
    interrupts whilst its clock is gated.

  - Power gated. This deepest state removes all power input to the core.
    All register state is lost and the core will restart execution from
    its BEV when another core powers it back up. Because register state
    is lost this state requires cooperation with the CONFIG_MIPS_CPS SMP
    implementation in order for the core to exit the state successfully.

The code will detect which states are available on the current system
during boot & generate the entry/exit code for those states. This will
be used by cpuidle & hotplug implementations.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The core which the CPC core-other region relates to is based upon the
core-local core-other addressing register. As its name suggests this
register is shared between all VPEs within a core, and if there is a
possibility that multiple VPEs within a core will attempt to access
another core simultaneously then locking is required. This wasn't
previously a problem with the only user being cpu0 during boot, but will
be an issue once hotplug is implemented & may race with other users such
as cpuidle.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The start of mips_cps_core_entry is patched in order to provide the code
with the address of the CM register region at a point where it will be
running non-coherent with the rest of the system. However the cache
wasn't being flushed after that patching which could in principle lead
to secondary cores using an invalid CM base address.

The patching is moved to cps_prepare_cpus since local_flush_icache_range
has not been initialised at the point cps_smp_setup is called.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The core power down state for cpuidle will require that the CPS SMP
implementation is in use. This patch provides a mips_cps_smp_in_use
function which determines whether or not the CPS SMP implementation is
currently in use.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

When hotplug and/or a powered down idle state are supported cases will
arise where a non-zero VPE must be brought online without VPE 0, and it
where multiple VPEs must be onlined simultaneously. This patch prepares
for that by:

  - Splitting struct boot_config into core & VPE boot config structures,
    allocated one per core or VPE respectively. This allows for multiple
    VPEs to be onlined simultaneously without clobbering each others
    configuration.

  - Indicating which VPEs should be online within a core at any given
    time using a bitmap. This allows multiple VPEs to be brought online
    simultaneously and also indicates to VPE 0 whether it should halt
    after starting any non-zero VPEs that should be online within the
    core. For example if all VPEs within a core are offlined via hotplug
    and the user onlines the second VPE within that core:

      1) The core will be powered up.

      2) VPE 0 will run from the BEV (ie. mips_cps_core_entry) to
         initialise the core.

      3) VPE 0 will start VPE 1 because its bit is set in the cores
         bitmap.

      4) VPE 0 will halt itself because its bit is clear in the cores
         bitmap.

  - Moving the core & VPE initialisation to assembly code which does not
    make any use of the stack. This is because if a non-zero VPE is to
    be brought online in a powered down core then when VPE 0 of that
    core runs it may not have a valid stack, and even if it did then
    it's messy to run through parts of generic kernel code on VPE 0
    before starting the correct VPE.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows use of the MT ASE yield instruction from uasm. It will
be used by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows use of the wait instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows use of the sync instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows use of the jalr instruction from uasm. It will be used
by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows for use of the beq instruction with labels from uasm,
much as bne & others already do. It will be used by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The opcode for the wait instruction within POOL32AXf was missing. This
patch adds it for use by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The opcode for the sync instruction within POOL32AXf was missing. This
patch adds it for use by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The opcode for the MT ASE yield instruction within the spec3 group was
missing. This patch adds it for use by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The func field for the wait instruction was missing from inst.h - this
patch adds it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Define a macro to write to the current TCs TCHalt register. This will be
used by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This is identical to kmap_coherent apart from the cache coherency
attribute used for the TLB entry, so kmap_coherent is abstracted to
kmap_prot which is then called for both kmap_coherent &
kmap_noncoherent. This will be used by a subsequent patch.
Suggested-by: Leonid Yegoshin <leonid.yegoshin@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch provides functions to lock & unlock access to the
"core-other" register region of the CPC. Without performing appropriate
locking it is possible for code using this region to be preempted or to
race with code on another VPE within the same core, with one changing
the core which the "core-other" region is acting upon at an inopportune
time for the other.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch introduces addr_ functions in addition to the existing read_
& write_ functions. The new functions simply return the address of the
appropriate CPC register rather than performing a memory access. This
will be used in a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Add a mask of CPUs which are currently known to be operating coherently.
This is setup initially to be all present CPUs, but in a subsequent
patch CPUs in a MIPS Coherent Processing System will be cleared in this
mask as they enter non-coherent idle states. This will be used in order
to determine when a CPU within a CPS system may need to be powered back
up, but may also be used in future to optimise away wakeups for cache
operations or TLB invalidations.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch adds support for generic clockevents broadcast using the a
dummy clockevent device and the tick_broadcast function introduced by
commit 12ad1000 "clockevents: Add generic timer broadcast function".
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Having the GIC clockevent driver compiled should not prevent the R4K
timer clockevent driver from functioning. One will be selected as the
CPU local timer based upon their priorities and the other may simply be
unused or in the case of the GIC timer may be used as the tick broadcast
device.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

The CLOCK_EVT_FEAT_PERCPU flag indicates that a clockevent device is
only configurable by the CPU for which it is registered, and thus cannot
be used as the tick broadcast device. That property is true of the R4K
timer, which is inaccessible from other cores.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

When a core enters a clock off or power down state its CP0 counter will
be stopped along with it.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

This patch allows the GIC clockevent device for a CPU to be configured
by another CPU. This makes GIC clockevent devices suitable for use as
the tick broadcast device, where formerly the GIC timer local to the
configuring CPU would have been configured incorrectly.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Although the GIC counter will continue when a core is in a low power
state and it will still trigger interrupts, the core will be incapable
of servicing those interrupts rendering them useless.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Implement assembler helper macros in asm/pm.h for platform code to use
for saving context across low power states - for example suspend to RAM
or powered down cpuidle states. Macros are provided for saving and
restoring the main CPU context used by C code and doing important
configuration which must be done very early during resume. Notably EVA
needs segmentation control registers to be restored before the stack or
dynamically allocated memory is accessed, so that state is saved in
global data.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Add a CPU power management callback for the r4k TLB which reconfigures
it after the CPU leaves a powered down state.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Implement a CPU power management callback for the r4k cache, to set up
coherency again after leaving a powered down state.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Implement a CPU power management callback for restoring trap related CPU
configuration after CPU power up from a low power state. The following
state is restored:

- Status register
- HWREna register
- Exception vector configuration registers
- Context/XContext register
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>

Add a CPU power management notifier callback for preserving general CPU
context. The CPU PM callbacks will be triggered by the powering down of
CPU cores, for example by cpuidle drivers & in the future by suspend to
RAM implementations.

The current state preserved is mostly related to the process context:
- FPU
- DSP
- ASID
- UserLocal
- Watch registers
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>