- 24 Apr, 2023 1 commit
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Andrew Halaney authored
Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by:
Stephen Boyd <sboyd@kernel.org> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by:
Brian Masney <bmasney@redhat.com> Signed-off-by:
Andrew Halaney <ahalaney@redhat.com> Signed-off-by:
Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413191541.1073027-2-ahalaney@redhat.com
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- 14 Apr, 2023 7 commits
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Konrad Dybcio authored
There's only one DSI PHY on this SoC. Remove the ghost entry for the clock produced by a secondary one. Fixes: cc517ea3 ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by:
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Shazad Hussain authored
Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by:
Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: make ready for upstream] Co-developed-by:
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by:
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Bartosz Golaszewski authored
Add the compatible for the Qualcomm Graphics Clock control module present on sa8775p platforms. It matches the generic QCom GPUCC description. Add device-specific DT bindings defines as well. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by:
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Dmitry Baryshkov authored
On SM8350 platform the PCIe PIPE clocks require additional handling to function correctly. They are to be switched to the tcxo source before turning PCIe GDSCs off and should be switched to PHY PIPE source once they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops, which provide support for this dance. Fixes: 44c20c9e ("clk: qcom: gcc: Add clock driver for SM8350") Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by:
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Mohammad Rafi Shaik authored
Add GDSCs in lpass_cc_sc7280_desc struct. When qcom,adsp-pil-mode is enabled, GDSCs required to solve dependencies in lpass_audiocc probe(). Fixes: 0cbcfbe5 ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon") Signed-off-by:
Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by:
Stephen Boyd <swboyd@chromium.org> Signed-off-by:
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Srinivasa Rao Mandadapu authored
The qdsp6ss memory region is being shared by ADSP remoteproc device and lpasscc clock device, hence causing memory conflict. To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and also assign max_register value. Fixes: 4ab43d17 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by:
Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by:
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Srinivasa Rao Mandadapu authored
When this property is set, the remoteproc is used to boot the LPASS and therefore qdsp6ss clocks would be used to bring LPASS out of reset, hence they are directly controlled by the remoteproc. This is a cleanup done to handle overlap of regmap of lpasscc and adsp remoteproc blocks. Signed-off-by:
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- 12 Apr, 2023 1 commit
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Lars-Peter Clausen authored
Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by:
Lars-Peter Clausen <lars@metafoo.de> Reviewed-by:
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- 07 Apr, 2023 5 commits
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Devi Priya authored
Add Global Clock Controller (GCC) driver for ipq9574 based devices Co-developed-by:
Anusha Rao <quic_anusha@quicinc.com> Signed-off-by:
Devi Priya <quic_devipriy@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge IPQ9574 Global Clock Controller binding through a topic branch to allow it also be introduced in the Devicetree source tree.
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Devi Priya authored
Add clock and reset ID definitions for ipq9574 Reviewed-by:
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Konrad Dybcio authored
Configure the disable wait value on the CX GDSC to ensure we don't get any undefined behavior. This was omitted when first adding the driver. Fixes: 8397e242 ("clk: qcom: Add GPU clock controller driver for SM6375") Signed-off-by:
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Konrad Dybcio authored
The vast majority of shared RCGs were not marked as such. Fix it. Fixes: cbe63bfd ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by:
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- 05 Apr, 2023 3 commits
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Konrad Dybcio authored
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by:
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Bjorn Andersson authored
Merge dt-binding include file additions through topic branch, to allow them to be made available in DT source tree as well.
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Konrad Dybcio authored
Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by:
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- 23 Mar, 2023 5 commits
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Kathiravan T authored
IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. To configure the stromer plus PLL separate API (clock_stromer_pll_configure) to be used. To achieve this, introduce the new member pll_type in device data structure and call the appropriate function based on this. Reviewed-by:
Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by:
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Kathiravan T authored
Add IPQ5332 compatible to A53 PLL bindings. Acked-by:
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Kathiravan T authored
APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But, IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs, refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver data. Reviewed-by:
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Krzysztof Kozlowski authored
The qcom,sdx55-apcs-gcc is followed by another compatible (syscon), thus the 'if' clause must match by contains. Fixes: 0d17014e ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by:
Rob Herring <robh@kernel.org> Acked-by:
Manivannan Sadhasivam <mani@kernel.org> Signed-off-by:
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Krzysztof Kozlowski authored
SDX55 and SDX65 DTS takes clocks in a bit different order. Adjust bindings to the DTS. Fixes: 0d17014e ("dt-bindings: mailbox: Add binding for SDX55 APCS") Signed-off-by:
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- 22 Mar, 2023 3 commits
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Konrad Dybcio authored
The USB controller on msm8998 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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Konrad Dybcio authored
The USB controller on MSM8996 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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Konrad Dybcio authored
The USB controller on sm6375 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by:
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- 16 Mar, 2023 5 commits
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Otto Pflüger authored
MSM8917 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and IPA_CLK and additionally has the BIMC_GPU clock. Signed-off-by:
Otto Pflüger <otto.pflueger@abscue.de> Reviewed-by:
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Otto Pflüger authored
This driver provides clocks, resets and power domains needed for various components of the MSM8917 SoC and the very similar QM215 SoC. According to [1] in the downstream kernel, the GPU clock has a different source mapping on QM215 (gcc_gfx3d_map vs gcc_gfx3d_map_qm215). [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.6.2-28000-89xx.0/include/dt-bindings/clock/msm-clocks-hwio-8952.h#L298Signed-off-by:
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Bjorn Andersson authored
Merge MSM8917 Global Clock Controller and RPM clock controller bindings through topic branch, to make it possible to introduce in Devicetree source depending on these.
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Otto Pflüger authored
Document the qcom,rpmcc-msm8917 compatible. Signed-off-by:
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Otto Pflüger authored
Add a device tree binding to describe clocks, resets and power domains provided by the global clock controller on MSM8917 SoCs and the very similar QM215 SoCs. Add the new compatibles to qcom,gcc-msm8909.yaml. There is no need to create another YAML file because the bindings are identical (MSM8917 GCC requires the same parent clocks as the MSM8909 GCC). Signed-off-by:
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- 15 Mar, 2023 10 commits
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Rayyan Ansari authored
Add the XO and XO_A clocks to the MSM8974 clock list, which is also used on MSM8226. Signed-off-by:
Rayyan Ansari <rayyan@ansari.sh> Tested-by:
Luca Weiss <luca@z3ntu.xyz> Reviewed-by:
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Christian Marangi authored
Rework kpss-gcc driver Documentation to yaml Documentation and move it to clock as it's a clock-controller. The current kpss-gcc Documentation have major problems and can't be converted directly. Introduce various changes to the original Documentation. Add #clock-cells additional binding as this clock outputs a static clk named acpu_l2_aux with supported compatible. Only some compatible require and outputs a clock, for the others, set only the reg as a required binding to correctly export the kpss-gcc registers. As the reg is shared also add the required syscon compatible. Signed-off-by:
Christian Marangi <ansuelsmth@gmail.com> Reviewed-by:
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Christian Marangi authored
Convert kpss-acc driver Documentation to yaml. The original Documentation was wrong all along. Fix it while we are converting it. The example was wrong as kpss-acc-v2 should only expose the regs but we don't have any driver that expose additional clocks. The kpss-acc driver is only specific to v1. For this exact reason, split the Documentation to 2 different schema, v1 as clock-controller and v2 for power-manager as per msm-3.10 specification, the exposed regs handle power manager. Signed-off-by:
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Kathiravan T authored
Clock framework disables the GPLL4 source since there are no active users for this source currently. Some of the clocks initialized by the bootloaders uses the GPLL4 as the source. Due to this, when the GPLL4 is disabled by the clock framework, system is going for the reboot. To avoid this, mark the GPLL4 as ignore unused so that clock framework doesn't disable it. Once the users of this source is enabled, we can get rid of this flag. Signed-off-by:
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Kathiravan T authored
Add support for the global clock controller found on IPQ5332 SoC. PLL used on IPQ5332 is of type Stromer Plus PLL, however the programming sequence is same as Stromer PLL, so lets re-use the Stromer PLL ops. Signed-off-by:
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Kathiravan T authored
Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by:
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Varadarajan Narayanan authored
Add programming sequence support for managing the Stromer PLLs. Reviewed-by:
Sricharan R <quic_srichara@quicinc.com> Signed-off-by:
Varadarajan Narayanan <quic_varada@quicinc.com> Signed-off-by:
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Bjorn Andersson authored
Merge the IPQ5332 Global Clock Controller binding through a topic branch to make it possible to include in Devicetree source as well.
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Kathiravan T authored
Add binding for the Qualcomm IPQ5332 Global Clock Controller. Reviewed-by:
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Tom Rix authored
gcc with W=1 reports these errors drivers/clk/qcom/gpucc-sm6375.c:145:37: error: ‘gpucc_parent_data_2’ defined but not used [-Werror=unused-const-variable=] 145 | static const struct clk_parent_data gpucc_parent_data_2[] = { | ^~~~~~~~~~~~~~~~~~~ drivers/clk/qcom/gpucc-sm6375.c:139:32: error: ‘gpucc_parent_map_2’ defined but not used [-Werror=unused-const-variable=] 139 | static const struct parent_map gpucc_parent_map_2[] = { | ^~~~~~~~~~~~~~~~~~ These variables are not used, so remove them. Signed-off-by:Tom Rix <trix@redhat.com> Reviewed-by:
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