- 01 Jul, 2021 2 commits
-
-
José Roberto de Souza authored
_DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one bit for phy C and D. Reusing _cnl_ddi_get_pll() don't take that into cosideration returing DPLL 0 and 1 for phy C and D. That is a regression introduced in the refactor done in commit 351221ff ("drm/i915: Move DDI clock readout to encoder->get_config()"). While at it also dropping the macros previously used, not reusing it to improve readability. BSpec: 50286 Fixes: 351221ff ("drm/i915: Move DDI clock readout to encoder->get_config()") Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Reviewed-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210630210522.162674-1-jose.souza@intel.com
-
Jani Nikula authored
Bring drm-intel-next closer to drm-next and drm-intel-gt-next for a more feasible baseline for topic branches. Signed-off-by:Jani Nikula <jani.nikula@intel.com>
-
- 30 Jun, 2021 3 commits
-
-
Bhanuprakash Modem authored
While reading the SDP infoframe, we are getting filtered with the encoder type INTEL_OUTPUT_DDI which causes the infoframe mismatch. This patch will drop encoder->type check as we can mask individual infoframe type. [1025.606556] i915 0000:00:02.0: [drm] *ERROR* mismatch in drm infoframe [1025.607865] i915 0000:00:02.0: [drm] *ERROR* expected: [1025.607879] i915 0000:00:02.0: HDMI infoframe: Dynamic Range and Mastering, version 1, length 26 [1025.607889] i915 0000:00:02.0: length: 26 [1025.607898] i915 0000:00:02.0: metadata type: 0 [1025.608292] i915 0000:00:02.0: eotf: 2 [1025.608302] i915 0000:00:02.0: x[0]: 35400 [1025.608312] i915 0000:00:02.0: y[0]: 14599 [1025.609115] i915 0000:00:02.0: x[1]: 8500 [1025.609947] i915 0000:00:02.0: y[1]: 39850 [1025.609959] i915 0000:00:02.0: x[2]: 6550 [1025.609970] i915 0000:00:02.0: y[2]: 2300 [1025.609980] i915 0000:00:02.0: white point x: 15634 [1025.609989] i915 0000:00:02.0: white point y: 16450 [1025.610381] i915 0000:00:02.0: max_display_mastering_luminance: 1000 [1025.610392] i915 0000:00:02.0: min_display_mastering_luminance: 500 [1025.610401] i915 0000:00:02.0: max_cll: 500 [1025.610816] i915 0000:00:02.0: max_fall: 1000 [1025.612457] i915 0000:00:02.0: [drm] *ERROR* found: [1025.614354] ------------[ cut here ]------------ [1025.616244] pipe state doesn't match! [1025.617640] WARNING: CPU: 6 PID: 2114 at drivers/gpu/drm/i915/display/intel_display.c:9332 intel_atomic_commit_tail+0x14d4/0x17c0 [i915] V2: * Drop encoder->type check V3: * Remove internal reviews Cc: Uma Shankar <uma.shankar@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Bhanuprakash Modem <bhanuprakash.modem@intel.com> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
-
Dave Airlie authored
Merge tag 'drm-intel-next-fixes-2021-06-29' of git://anongit.freedesktop.org/drm/drm-intel into drm-next The biggest fix is the restoration of mmap ioctl for gen12 integrated parts which lack was breaking ADL-P with media stack. Besides that a small selftest fix and a theoretical overflow on i915->pipe_to_crtc_mapping. Signed-off-by:
Dave Airlie <airlied@redhat.com> From: Rodrigo Vivi <rodrigo.vivi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/YNtsfguvCRSROBUZ@intel.com
-
Dave Airlie authored
Merge tag 'drm-misc-next-fixes-2021-06-24' of git://anongit.freedesktop.org/drm/drm-misc into drm-next Short summary of fixes pull: * amdgpu: Fix test for allocation failures Signed-off-by:
-
- 29 Jun, 2021 2 commits
-
-
Tejas Upadhyay authored
Removing force probe protection from EHL platform. Did not observe warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results : https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html? Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Tejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
-
Tejas Upadhyay authored
Removing force probe protection from JSL platform. Did not observe warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. For more info drm-tip idle run results : https://intel-gfx-ci.01.org/tree/drm-tip/drmtip.html? Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
- 28 Jun, 2021 2 commits
-
-
Thomas Hellström authored
Reinstate the mmap ioctl for all current integrated platforms. The intention was really to have it disabled for discrete graphics where we enforce a single mmap mode. This was reported to break ADL-P with the media stack, which was not the intention. Although longer term we do still plan to sunset this ioctl even for integrated, in favour of using mmap_offset instead. Fixes: 35cbd91e ("drm/i915: Disable mmap ioctl for gen12+") Signed-off-by:
Thomas Hellström <thomas.hellstrom@linux.intel.com> Reviewed-by:
Matthew Auld <matthew.auld@intel.com> Acked-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
-
Jani Nikula authored
Add a single point of truth for figuring out the primary/secondary crtc for bigjoiner instead of duplicating the magic pipe +/- 1 in multiple places. Also fix the pipe validity checks to properly take non-contiguous pipes into account. The current checks may theoretically overflow i915->pipe_to_crtc_mapping[pipe], albeit with a warning, due to fused off pipes, as INTEL_NUM_PIPES() returns the actual number of pipes on the platform, and the check is for INTEL_NUM_PIPES() == pipe + 1. Prefer primary/secondary terminology going forward. v2: - Improved abstractions for pipe validity etc. Fixes: 8a029c11 ("drm/i915/dp: Modify VDSC helpers to configure DSC for Bigjoiner slave") Fixes: d961eb20 ("drm/i915/bigjoiner: atomic commit changes for uncompressed joiner") Cc: Animesh Manna <animesh.manna@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Reviewed-by:
Manasi Navare <manasi.dl.navare@intel.com> Signed-off-by:
-
- 25 Jun, 2021 2 commits
-
-
Lucas De Marchi authored
Since we are already loop through the levels to sanitize them, mark what is the real max_level so it can be used in subsequent loop. This makes it simpler to later add the adjustment latency to "valid levels". No change in behavior, just makes the code easier to follow. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210622212210.3746133-2-lucas.demarchi@intel.com
-
Lucas De Marchi authored
We should no longer increment level 0 by 1usec when we have 16Gb DIMMs. Instead spec says to add 3usec (as opposed to 2) to each valid level when punit replies 0 to level 0. So set wm_lv_0_adjust_needed to false for DISPLAY_VER() >= 12 and set the proper adjustment value when handling WaWmMemoryReadLatency. Bspec: 49326, 4381 Signed-off-by:
-
- 24 Jun, 2021 25 commits
-
-
José Roberto de Souza authored
PSR2 is not compatible with DC3CO or VRR in this stepping, so not enabling PSR2 if VRR will be enabled or not enabling DC3CO if PSR2 is possible. BSpec: 54369 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210616203158.118111-5-jose.souza@intel.com
-
José Roberto de Souza authored
In some modes there is not enough time during hblank to transmit PSR2 SDP plus the pixels CRC SDP, if such case happens PSR2 needs to be disabled. But eDP spec 1.4b allows to transmit PSR2 SDP in a prior scanline alone and than later the CRC SDP, allowing PSR2 to be enabled in those hblank constrained modes. BSpec: 49274 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
-
José Roberto de Souza authored
Another WA that is required for PSR2. BSpec: 54369 Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Cc: Matt Atwood <matthew.s.atwood@intel.com> Signed-off-by:
-
José Roberto de Souza authored
The PSR2_CTL io buffer wake and fast wake values do not match expected in pre production hardware, so here adding a table that matches with HW to program it with values that HW expect. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
-
José Roberto de Souza authored
We were only handling X and width granularity, what was causing issues when sink had a granularity different than 4. While at it, renaming su_x_granularity to su_w_granularity to better match reality. Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> Signed-off-by:
-
Ville Syrjälä authored
Clear out the straggler 'intel_crtc' variables. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210609085632.22026-7-ville.syrjala@linux.intel.comReviewed-by:
-
Ville Syrjälä authored
Sort out the mess with the local variables in intel_fbdev_init_bios(). Get rid of all aliasing pointers, use standard naming/types, and introduce a few more locals in the loops to avoid the hard to read long struct walks. While at we also polish the debugs a bit to use the canonical [CRTC:%d:%s] style. Signed-off-by:
-
Ville Syrjälä authored
Just pass the full atomic state+crtc to the pre-skl watermark functions, and clean up the types/variable names around the area. Note that having both .compute_pipe_wm() and .compute_intermediate_wm() is entirely redundant now. We could unify them to a single vfunc. But let's do this one step at a time. Signed-off-by:
-
Ville Syrjälä authored
Sort out the mess with the local variables in intel_find_initial_plane_obj(). Get rid of all aliasing pointers and use standard naming/types. Signed-off-by:
-
Ville Syrjälä authored
Sort out the mess with the local variables in intel_get_load_detect_pipe(). Get rid of all aliasing pointers and use standard naming/types. Signed-off-by:
-
Ville Syrjälä authored
Use drm_crtc_mask() instead of hand rolling it. Signed-off-by:
-
Ville Syrjälä authored
Since the llb allocation has a fixed size, let's grab it before the potentially variable sized cfb. That should avoid some allocation failure cases once we allow different compression ratios for FBC1. Signed-off-by:
-
Ville Syrjälä authored
Write the cfb allocation loop as an actual loop instead of some hard to read goto thing. Signed-off-by:
-
Ville Syrjälä authored
Declutter find_compression_limit() a bit by extracting intel_fbc_stolen_end(). Signed-off-by:
-
Ville Syrjälä authored
Exctract the limit->register value conversion into a common helper. Signed-off-by:
-
Ville Syrjälä authored
The limit++ for the 16bpp case is nonsense since the compression limit is always supposed to be power of two. Replace it with <<=1. Signed-off-by:
-
Ville Syrjälä authored
No point in passing the mm node explicitly to find_compression_limit() since it's always the same node for the cfb. Signed-off-by:
-
Ville Syrjälä authored
Not much point in dynamically allocating the line length buffer mm node that I can see. Just embed it directly like we do the for the cfb node. One less failure point to worry about. Signed-off-by:
-
Ville Syrjälä authored
Extract the CFB (+LLB) programming into a separate function. Signed-off-by:
-
Ville Syrjälä authored
Let's call the compression limit the limit. Signed-off-by:
-
Ville Syrjälä authored
adls is supposed to use special buf trans tables. Add what's missing. v2: Drop the RBR/HBR table since it's the same as for tgl Signed-off-by:
-
Ville Syrjälä authored
All the foo_get_buf_trans_hdmi() functions just return a single table. Remove the pointless wrappers. v2: Handle adl-p Signed-off-by:
-
Ville Syrjälä authored
The jsl/ehl buf trans functions are needlessly complicated. Simplify them. Signed-off-by:
-
Ville Syrjälä authored
EHL is supposed to use special buf trans values for eDP HBR2+. Add such a table. Signed-off-by:
-
Lee Shawn C authored
This workaround is specific for a particular panel on Google chromebook project. When user space daemon enter idle state. It request adjust brightness to 0, turn backlight_enable signal off and keep eDP main link active. On general LCD, this behavior might not be a problem. But on this panel, its tcon would expect source to execute full eDP power off sequence after drop backlight_enable signal. Without eDP power off sequence. Even source try to turn backlight_enable signal on and restore proper brightness level. This panel is not able to light on again. This WA ignored the request from user space daemon to disable backlight_enable signal and keep it on always. When user space request kernel to turn eDP display off, kernel driver still can control backlight_enable signal properly. It would not impact standard eDP power off sequence. v2: 1. modify the quirk name and debug messages. 2. unregister backlight.power callback for specific device. v3: 1. modify debug output messages. 2. use DMI_EXACT_MATCH instead of DMI_MATCH. Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Cooper Chiou <cooper.chiou@intel.com> Signed-off-by:Lee Shawn C <shawn.c.lee@intel.com> Signed-off-by:
-
- 23 Jun, 2021 4 commits
-
-
Dave Airlie authored
Merge tag 'amd-drm-next-5.14-2021-06-22-1' of https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-22-1: amdgpu: - Userptr BO fixes - RAS fixes - Beige Goby fixes - Add some missing freesync documentation - Aldebaran fixes - SR-IOV fixes - Potential memory corruption fix in framebuffer handling - Revert GFX9, 10 doorbell fixes, we just end up trading one bug for another - Multi-plane cursor fixes with rotation - LTTPR fixes - Backlight fixes - eDP fix - Fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN - Misc code cleanups amdkfd: - Topology fix - Locking fix radeon: - Misc code cleanup Signed-off-by:
-
https://gitlab.freedesktop.org/drm/msmDave Airlie authored
* devcoredump support for display errors * dpu: irq cleanup/refactor * dpu: dt bindings conversion to yaml * dsi: dt bindings conversion to yaml * mdp5: alpha/blend_mode/zpos support * a6xx: cached coherent buffer support * a660 support * gpu iova fault improvements: - info about which block triggered the fault, etc - generation of gpu devcoredump on fault * assortment of other cleanups and fixes Signed-off-by:
-
Rob Clark authored
This reverts commit c1d12c19. Breaks armv7 build ERROR: modpost: "__aeabi_ldivmod" [drivers/gpu/drm/msm/msm.ko] undefined! Signed-off-by:
Rob Clark <robdclark@chromium.org>
-
Dmitry Baryshkov authored
Instead of using static bandwidth setup, manage bandwidth dynamically, depending on the amount of allocated planes, their format and resolution. Co-developed-with: James Willcox <jwillcox@squareup.com> Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by:
kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/r/20210525131316.3117809-8-dmitry.baryshkov@linaro.orgSigned-off-by:
-
