- 12 May, 2014 1 commit
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Jean Delvare authored
Anyone working with an AMD Elan SC520 development or evaluation board would be building a dedicated kernel for it, so we can make the sc520cdp and netsc520 maps depend on MELAN. SC520_CPUFREQ already depends on MELAN so it makes things more consistent. It also makes kernel configuration for every other x86 user easier. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Cc: David Woodhouse <dwmw2@infradead.org> Signed-off-by:
Brian Norris <computersforpeace@gmail.com>
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- 09 May, 2014 1 commit
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Brian Norris authored
The nand_chip::erase_cmd callback previously served a dual purpose; for one, it allowed a per-flash-chip override, so that AG-AND devices could use a different erase command than other NAND. These AND devices were dropped in commit 14c65786 (mtd: nand: remove AG-AND support). On the other hand, some drivers (denali and doc-g4) need to use this sort of callback to implement controller-specific erase operations. To make the latter operation easier for some drivers (e.g., ST's new BCH NAND driver), it helps if the command dispatch and wait functions can be lumped together, rather than called separately. This patch does two things: 1. Pull the call to chip->waitfunc() into chip->erase_cmd(), and return the status from this callback 2. Rename erase_cmd() to just erase(), since this callback does a little more than just send a command Signed-off-by:
Lee Jones <lee.jones@linaro.org>
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- 29 Apr, 2014 1 commit
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Masahiro Yamada authored
Signed-off-by:
Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by:
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- 18 Apr, 2014 1 commit
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Akinobu Mita authored
mtd_oobtest writes OOB, read it back and verify. The verification is not correctly done if oobsize is not multiple of 4. Although the data to be written and the data to be compared are generated by several prandom_byte_state() calls starting with the same seed, these two are generated with the different size and different number of calls. Due to the implementation of prandom_byte_state() if the size on each call is not multiple of 4, the resulting data is not always same. This fixes it by just calling prandom_byte_state() once and using correct range instead of calling it multiple times for each. Reported-by:
George Cherian <george.cherian@ti.com> Reported-by:
Lothar Waßmann <LW@KARO-electronics.de> Tested-by:
Akinobu Mita <akinobu.mita@gmail.com> Signed-off-by:
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- 17 Apr, 2014 3 commits
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Brian Norris authored
Addition of the spi-nor framework, plus updates to the ST SPI FSM driver.
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Brian Norris authored
COMPILE_TEST allows us to build this driver on other arch'es. But not all arch'es have the right I/O accessors -- particularly, x86 is missing readsl() and writesl(). So just restrict this driver to ARCH_STI. It's still buildable for a multiplatform ARM kernel, so it can get decent compile coverage. Signed-off-by:
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Brian Norris authored
Compile-testing for a 64-bit arch uncovers several bad casts: In file included from include/linux/linkage.h:4:0, from include/linux/kernel.h:6, from drivers/mtd/devices/st_spi_fsm.c:15: drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_read_fifo’: drivers/mtd/devices/st_spi_fsm.c:758:11: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] BUG_ON((((uint32_t)buf) & 0x3) || (size & 0x3)); ... Use uintptr_t instead of uint32_t, since it's guaranteed to be pointer-sized. We also see this warning, if size_t is not 32 bits wide: In file included from drivers/mtd/devices/st_spi_fsm.c:15:0: drivers/mtd/devices/st_spi_fsm.c: In function ‘stfsm_mtd_write’: include/linux/kernel.h:712:17: warning: comparison of distinct pointer types lacks a cast [enabled by default] (void) (&_min1 == &_min2); \ ^ drivers/mtd/devices/st_spi_fsm.c:1704:11: note: in expansion of macro ‘min’ bytes = min(FLASH_PAGESIZE - page_offs, len); ^ Just use min_t() to force the type conversion, since we don't really want to upgrade 'page_offs' and 'bytes' to size_t; they only should be handling <= 256 byte offsets. Signed-off-by:
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- 16 Apr, 2014 7 commits
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Brian Norris authored
This corrects some sparse warnings: drivers/mtd/spi-nor/fsl-quadspi.c:281:31: warning: incorrect type in initializer (different address spaces) [sparse] drivers/mtd/spi-nor/fsl-quadspi.c:281:31: expected void *[noderef] <asn:2>base [sparse] drivers/mtd/spi-nor/fsl-quadspi.c:281:31: got void [noderef] <asn:2>*iobase [sparse] (etc.) Signed-off-by:
Huang Shijie <b32955@freescale.com>
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Huang Shijie authored
More and more chips use the GPMI controller, but these chips may use different version of the IPs for GPMI and BCH. Different IPs have different features, such as the BCH's maximum ECC strength: imx23/imx28 -- the BCH's maximum ECC strength is 20 imx6q -- the BCH's maximum ECC strength is 40 imx6sx -- the BCH's maximum ECC strength is 62 This patch does the following things: [1] add a new data structure, gpmi_devdata{}, to store the information for each IP. Besides the IP version, we store the following information: <1> BCH's maximum ECC strength. <2> the maximum chain delay in ns used by the EDO mode. but we may add more information in future. [2] add the gpmi_devdata_imx{23|28|6q} to replace the gpmi_ids. [3] simplify the code by using the ECC strength from gpmi_devdata, such as gpmi_check_ecc() and legacy_set_geometry(); [4] use the maximum chain delay to initialize the EDO mode, see gpmi_compute_edo_timing(). [5] rewrite the macros, such GPMI_IS_MX{23|28|6Q}. Signed-off-by: -
Raphaël Poggi authored
Add line feed to pr_err. Signed-off-by:
Raphaël Poggi <poggi.raph@gmail.com> Signed-off-by:
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Murali Karicheri authored
Sub page write doesn't work because of hw issue in controller found on Keystone SOCs. AEMIF controller is also used on DaVinci SOCs which don't seems to have any issue. So add "ti,keysone-nand" compatible to nand driver in order to set NAND_NO_SUBPAGE_WRITE option. Cc: Warner Losh <imp@bsdimp.com> Signed-off-by:
Murali Karicheri <m-karicheri2@ti.com> Signed-off-by:
Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Acked-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
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Roman Peniaev authored
mtd_blkdevs is device with volatile cache (writeback buffer), so it should support REQ_FLUSH to do explicit flush. Without this patch 'sync' does not guarantee that writeback buffer will be flushed on disk in case of power off, e.g.: $ cp some_file /mnt $ sync ### POWER OFF In case of this sequence writeback buffer will not be flushed on disk. This patch fixes this behaviour and explicitly reports to block layer that flush requests are being supported. Signed-off-by:
Roman Peniaev <r.peniaev@gmail.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by:
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Ron authored
Now that the index variable is correctly set earlier in this function we can use it in other places that compute the same thing too. Signed-off-by:
Ron Lee <ron@debian.org> Signed-off-by:
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Christian Engelmayer authored
Commit 2c9f2365 (mtd: nand: omap: ecc.calculate: merge omap3_calculate_ecc_bch4 in omap_calculate_ecc_bch) introduced minor compile warning "‘erased_sector_bitflips’ defined but not used [-Wunused-function]" when compiling without CONFIG_MTD_NAND_OMAP_BCH. Move function erased_sector_bitflips() into the same ifdef section as the only caller. Signed-off-by:
Christian Engelmayer <cengelma@gmx.at> Reviewed-by:
Jingoo Han <jg1.han@samsung.com> Acked-by:
Pekon Gupta <pekon@ti.com> Signed-off-by:
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- 14 Apr, 2014 26 commits
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Brian Norris authored
There's no reason this can't be a module. Also, give SPI-NOR its own submenu. Signed-off-by:
Marek Vasut <marex@denx.de>
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Brian Norris authored
Many of the serial_flash_cmds.h opcodes are duplicated with spi-nor.h. Let's begin to unify them. Signed-off-by:
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Brian Norris authored
Begin to unify the differences between serial_flash_cmds.h and spi-nor.h. Signed-off-by:
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Brian Norris authored
These are also in serial_flash_cmds.h. (FWIW, I didn't know the C preprocessor allowed redefinitions without warning like this.) Signed-off-by:
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Brian Norris authored
I hear that this driver should depend on ARCH_STI, and that "SH" is not actually a real symbol. At the same time, let's allow compile-testing on other ARCH'es. Signed-off-by:
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Brian Norris authored
Signed-off-by:
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Brian Norris authored
Signed-off-by:
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Brian Norris authored
serial_flash_cmds.h defines our opcodes a little differently. Let's borrow its naming, since it's borrowed from the SFDP standard, and it's more extensible. This prepares us for merging serial_flash_cmds.h and spi-nor.h opcode listing. Signed-off-by:
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Brian Norris authored
Qualify these with a better namespace, and prepare them for use in more drivers. Signed-off-by:
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Brian Norris authored
Spacing is a little non-standard here. Fix up tabs vs. spaces. Signed-off-by:
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Huang Shijie authored
Add the copyright information for spi-nor.c and spi-nor.h. Signed-off-by:
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Angus Clark authored
This patch adds support for the Macronix MX25L3255E device. Unlike the other Macronix devices we have seen, this device supports WRITE_1_4_4 at reasonable frequencies. Rather than masking out WRITE_1_4_4 support altogether, we now rely on the table parameters to indicate whether or not WRITE_1_4_4 should be used. Signed-off-by:
Angus Clark <angus.clark@st.com> Signed-off-by:
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Angus Clark authored
Add Spansion S25FL032P to the list of known devices. Signed-off-by:
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Angus Clark authored
This patch refactors the fsm_read_status() and fsm_write_status() code to support 1 or 2 byte operations, with a specified command. This allows us to remove device/register specific code, such as the N25Q fsm_wrvcr() function. The 'QE' configuration code is updated accordingly, with minor tweaks to ensure the register values are only written if actually required. One notable change in this area is that the 'W25Q_STATUS_QE' bit-field is now defined with respect to the 'SR2' register, rather than the combined 'SR1+SR2' register which is only used for write operations. Signed-off-by:
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Angus Clark authored
Update the configuration of the Macronix 'QE' bit, such that we only set or clear the bit if required. Signed-off-by:
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Angus Clark authored
Support for the Macronix 32-bit addressing scheme was originally developed using the MX25L25635E device. As is often the case, it was found that the presence of a "WAIT" instruction was required for the "EN4B/EX4B" FSM Sequence to complete. (It is known that the SPI FSM Controller makes certain undocumented assumptions regarding what constitutes a valid sequence.) However, further testing suggested that a small delay was required after issuing the "EX4B" command; without this delay, data corruptions were observed, consistent with the device not being ready to retrieve data. Although the issue was not fully understood, the workaround of adding a small delay was implemented, while awaiting clarification from Macronix. The same behaviour has now been found with a second Macronix device, the MX25L25655E. However, with this device, it seems that the delay is also required after the 'EN4B' commands. This discovery has prompted us to revisit the issue. Although still not conclusive, further tests have suggested that the issue is down to the SPI FSM Controller, rather than the Macronix devices. Furthermore, an alternative workaround has emerged which is to set the WAIT time to 0x00000001, rather then 0x00000000. (Note, the WAIT instruction is used purely for the purpose of achieving "sequence validity", rather than actually implementing a delay!) The issue is now being investigated by the Design and Validation teams. In the meantime, we implement the alternative workaround, which reduces the effective delay from 1us to 1ns. Signed-off-by:
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Angus Clark authored
Add Macronix MX25L25655E to the list of known devices. Signed-off-by:
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Brian Norris authored
Fix errors like this: ERROR: "spi_nor_ids" [drivers/mtd/devices/m25p80.ko] undefined! ERROR: "spi_nor_scan" [drivers/mtd/devices/m25p80.ko] undefined! make[1]: *** [__modpost] Error 1 make: *** [modules] Error 2 Signed-off-by: -
Huang Shijie authored
(0) What is the QuadSPI controller? The QuadSPI(Quad Serial Peripheral Interface) acts as an interface to one single or two external serial flash devices, each with up to 4 bidirectional data lines. (1) The QuadSPI controller is driven by the LUT(Look-up Table) registers. The LUT registers are a look-up-table for sequences of instructions. A valid sequence consists of four LUT registers. (2) The definition of the LUT register shows below: --------------------------------------------------- | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 | --------------------------------------------------- There are several types of INSTRx, such as: CMD : the SPI NOR command. ADDR : the address for the SPI NOR command. DUMMY : the dummy cycles needed by the SPI NOR command. .... There are several types of PADx, such as: PAD1 : use a singe I/O line. PAD2 : use two I/O lines. PAD4 : use quad I/O lines. .... (3) Test this driver with the JFFS2 and UBIFS: For jffs2: ------------- #flash_eraseall /dev/mtd0 #mount -t jffs2 /dev/mtdblock0 tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 For ubifs: ------------- #flash_eraseall /dev/mtd0 #ubiattach /dev/ubi_ctrl -m 0 #ubimkvol /dev/ubi0 -N test -m #mount -t ubifs ubi0:test tmp #bonnie++ -d tmp -u 0 -s 10 -r 5 Signed-off-by: -
Huang Shijie authored
This patch adds the binding file for Freescale QuadSPI driver. Signed-off-by:
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Huang Shijie authored
Add the spi_nor_match_id() to find the proper spi_device_id with the NOR flash's name in the spi_nor_ids table. Signed-off-by:
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Brian Norris authored
Use the new SPI nor framework, and rewrite the m25p80: (0) remove all the NOR comands. (1) change the m25p->command to an array. (2) implement the necessary hooks, such as m25p80_read/m25p80_write. Tested with the m25p32. Signed-off-by:
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Huang Shijie authored
This patch adds the document for the SPI NOR framework. Signed-off-by:
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Huang Shijie authored
This patch cloned most of the m25p80.c. In theory, it adds a new spi-nor layer. Before this patch, the layer is like: MTD ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip After this patch, the layer is like: MTD ------------------------ spi-nor ------------------------ m25p80 ------------------------ spi bus driver ------------------------ SPI NOR chip With the spi-nor controller driver(Freescale Quadspi), it looks like: MTD ------------------------ spi-nor ------------------------ fsl-quadspi ------------------------ SPI NOR chip New APIs: spi_nor_scan: used to scan a spi-nor flash. Signed-off-by: -
Huang Shijie authored
The spi_nor{} is cloned from the m25p{}. The spi_nor{} can be used by both the m25p80 and spi-nor controller. We also add the spi_nor_xfer_cfg{} which can be used by the two fundamental primitives: read_xfer/write_xfer. 1) the hooks for spi_nor{}: @prepare/unpreare: used to do some work before or after the read/write/erase/lock/unlock. @read_xfer/write_xfer: We can use these two hooks to code all the following hooks if the driver tries to implement them by itself. @read_reg: used to read the registers, such as read status register, read configure register. @write_reg: used to write the registers, such as write enable, erase sector. @read_id: read out the ID info. @wait_till_ready: wait till the NOR becomes ready. @read: read out the data from the NOR. @write: write data to the NOR. @erase: erase a sector of the NOR. 2) Add a new field sst_write_second for the SST NOR write. Signed-off-by: -
Huang Shijie authored
This patch adds a new header :spi-nor.h, and copies all the SPI NOR commands and relative macros into this new header. This hearder can be used by the m25p80.c and other spi-nor controller, such as Freescale's Quadspi. Signed-off-by:
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