- 07 Aug, 2018 3 commits
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Paul Burton authored
The code in __write_64bit_c0_split() is used by MIPS32 kernels running on MIPS64 CPUs to write a 64-bit value to a 64-bit coprocessor 0 register using a single 64-bit dmtc0 instruction. It does this by combining the 2x 32-bit registers used to hold the 64-bit value into a single register, which in the existing code involves three steps: 1) Zero extend register A which holds bits 31:0 of our data, since it may have previously held a sign-extended value. 2) Shift register B which holds bits 63:32 of our data in bits 31:0 left by 32 bits, such that the bits forming our data are in the position they'll be in the final 64-bit value & bits 31:0 of the register are zero. 3) Or the two registers together to form the 64-bit value in one 64-bit register. From MIPS r2 onwards we have a dins instruction which can effectively perform all 3 of those steps using a single instruction. Add a path for MIPS r2 & beyond which uses dins to take bits 31:0 from register B & insert them into bits 63:32 of register A, giving us our full 64-bit value in register A with one instruction. Since we know that MIPS r2 & above support the sel field for the dmtc0 instruction, we don't bother special casing sel==0. Omiting the sel field would assemble to exactly the same instruction as when we explicitly specify that it equals zero. Signed-off-by:Paul Burton <paul.burton@mips.com>
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Paul Burton authored
Commit c22c8043 ("MIPS: Fix input modify in __write_64bit_c0_split()") modified __write_64bit_c0_split() constraints such that we have both an input & an output which we hope to assign to the same registers, and modify the output rather than incorrectly clobbering an input. The way in which we use both an output & an input parameter with the input constrained to share the output registers is a little convoluted & also problematic for clang, which complains if the input & output values have different widths. For example: In file included from kernel/fork.c:98: ./arch/mips/include/asm/mmu_context.h:149:19: error: unsupported inline asm: input with type 'unsigned long' matching output with type 'unsigned long long' write_c0_entryhi(cpu_asid(cpu, next)); ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ ./arch/mips/include/asm/mmu_context.h:93:2: note: expanded from macro 'cpu_asid' (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu])) ^ ./arch/mips/include/asm/mipsregs.h:1617:65: note: expanded from macro 'write_c0_entryhi' #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~ ./arch/mips/include/asm/mipsregs.h:1430:39: note: expanded from macro '__write_ulong_c0_register' __write_64bit_c0_register(reg, sel, val); \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~ ./arch/mips/include/asm/mipsregs.h:1400:41: note: expanded from macro '__write_64bit_c0_register' __write_64bit_c0_split(register, sel, value); \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ ./arch/mips/include/asm/mipsregs.h:1498:13: note: expanded from macro '__write_64bit_c0_split' : "r,0" (val)); \ ^~~ We can both fix this build failure & simplify the code somewhat by assigning the __tmp variable with the input value in C prior to our inline assembly, and then using a single read-write output operand (ie. a constraint beginning with +) to provide this value to our assembly. Signed-off-by:
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Paul Burton authored
Passing an array (swapper_pg_dir) as the argument to write_c0_kpgd() in setup_pw() will become problematic if we modify __write_64bit_c0_split() to cast its val argument to unsigned long long, because for 32-bit kernel builds the size of a pointer will differ from the size of an unsigned long long. This would fall foul of gcc's pointer-to-int-cast diagnostic. Cast the value to a long, which should be the same width as the pointer that we ultimately want & will be sign extended if required to the unsigned long long that __write_64bit_c0_split() ultimately needs. Signed-off-by:
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- 06 Aug, 2018 3 commits
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Paul Burton authored
The MIPS VDSO code filters out a subset of known-good flags from KBUILD_CFLAGS to use when building VDSO libraries. When we build using clang we need to allow the --target flag through, otherwise we'll generally attempt to build the VDSO for the architecture of the build machine rather than for MIPS. Signed-off-by:
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Paul Burton authored
Our genvdso tool performs some rather paranoid checking that the VDSO library isn't attempting to make use of a GOT by constraining the number of entries that the GOT is allowed to contain to the minimum 2 entries that are always generated by binutils. Unfortunately lld prior to revision 334390 generates a third entry, which is unused & thus harmless but falls foul of genvdso's checks & causes the build to fail. Since we already check that the VDSO contains no relocations it seems reasonable to presume that it also doesn't contain use of a GOT, which would involve relocations. Thus rather than attempting to work around this issue by allowing 3 GOT entries when using lld, simply remove the GOT checks which seem overly paranoid. Signed-off-by:
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Robert P. J. Day authored
As there is precious little left in any DTS files referring to the node "/chosen@0" as opposed to "/chosen", remove the two checks for the former node name. [paul.burton@mips.com: The modified yamon-dt code only operates on arch/mips/boot/dts/mti/sead3.dts right now, and that uses chosen rather than chosen@0 anyway, so this should have no behavioural effect.] Signed-off-by:
Robert P. J. Day <rpjday@crashcourse.ca> Signed-off-by:
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- 02 Aug, 2018 1 commit
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Paul Burton authored
generic_defconfig explicitly disables CONFIG_INPUT_MOUSEDEV, CONFIG_INPUT_KEYBOARD & CONFIG_INPUT_MOUSE which results in warnings when merging board config fragments if any of them require these options. This is the case for the ranchu board, which means we've had the following warning when configuring for generic platform targets since commit f2d0b0d5 ("MIPS: ranchu: Add Ranchu as a new generic-based board"): $ make ARCH=mips 32r2el_defconfig Using ./arch/mips/configs/generic_defconfig as base Merging arch/mips/configs/generic/32r2.config Merging arch/mips/configs/generic/el.config Merging ./arch/mips/configs/generic/board-sead-3.config Merging ./arch/mips/configs/generic/board-ranchu.config Value of CONFIG_INPUT_KEYBOARD is redefined by fragment ./arch/mips/configs/generic/board-ranchu.config: Previous value: # CONFIG_INPUT_KEYBOARD is not set New value: CONFIG_INPUT_KEYBOARD=y Merging ./arch/mips/configs/generic/board-ni169445.config Merging ./arch/mips/configs/generic/board-boston.config Merging ./arch/mips/configs/generic/board-ocelot.config Merging ./arch/mips/configs/generic/board-xilfpga.config scripts/kconfig/conf --olddefconfig Kconfig # # configuration written to .config # Resolve this by removing mention of the CONFIG_INPUT_* Kconfig symbols from generic_defconfig, allowing them to take their default values & allowing board config fragments to enable them without warnings. This may be problematic if CONFIG_ARCH_MIGHT_HAVE_PC_SERIO is ever enabled for CONFIG_MIPS_GENERIC=y configurations, but for now that isn't the case so we can worry about that if & when it happens. Signed-off-by:
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- 01 Aug, 2018 3 commits
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Paul Burton authored
The A() & AA() macros have been unused since commit 05e43966 ("[MIPS] Use SYSVIPC_COMPAT to fix various problems on N32"), which switched to the more standard compat_ptr(). RLIM_INFINITY32, RESOURCE32() & struct rlimit32 have been present but unused since the beginning of the git era. Remove the dead code. Signed-off-by:
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Paul Burton authored
The sys_32_mmap2 function has been unused since we started using syscall wrappers in commit dbda6ac0 ("MIPS: CVE-2009-0029: Enable syscall wrappers."), and is indeed identical to the sys_mips_mmap2 function that replaced it in sys32_call_table. Remove the dead code. Signed-off-by:
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Paul Burton authored
Our sigreturn functions make use of a macro named nabi_no_regargs to declare 8 dummy arguments to a function, forcing the compiler to expect a pt_regs structure on the stack rather than in argument registers. This is an ugly hack which unnecessarily causes these sigreturn functions to need to care about the calling convention of the ABI the kernel is built for. Although this is abstracted via nabi_no_regargs, it's still ugly & unnecessary. Remove nabi_no_regargs & the struct pt_regs argument from sigreturn functions, and instead use current_pt_regs() to find the struct pt_regs on the stack, which works cleanly regardless of ABI. Signed-off-by:
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- 31 Jul, 2018 4 commits
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Alexandre Belloni authored
Ocelot PCB123 has a SPI NOR connected on its SPI bus. Signed-off-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
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Alexandre Belloni authored
Add support for the SPI controller Signed-off-by:
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谢致邦 (XIE Zhibang) authored
Systems based upon the Loongson 1B & 1C CPUs share the same load address, as do those based upon Loongson 1A. Unify the definition of this load address to reduce duplication & avoid the need for an extra Loongson 1A case in future. [paul.burton@mips.com: Rewrite commit message.] Signed-off-by:
谢致邦 (XIE Zhibang) <Yeking@Red54.com> Signed-off-by:
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谢致邦 (XIE Zhibang) authored
LS232 (Loonson 2-issue 32-bit, also called GS232 (Godson 2-issue 32-bit)) is the CPU core (microarchitecture) of Loongson 1A/1B/1C. According to "LS232 用户手册 (LS232 User Manual)", LS232 implements the MIPS32 Release 1 instruction set, and part of the MIPS32 Release 2 instruction set. In the manual, LS232 implements all of the MIPS32R2 instruction set except the FPU instructions, and LS232 also implements 5 FPU instructions of the MIPS32R2 instruction set: CEIL.L.fmt, CVT.L.fmt, FLOOR.L.fmt, TRUNC.L.fmt, and ROUND.L.fmt. But a bug of the DI instruction has been found during tests, the DI instruction can not disable interrupts in arch_local_irq_disable() with CONFIG_PREEMPT_NONE=y and CFLAGS='-mno-branch-likely' in some cases. [paul.burton@mips.com: - Remove the _MIPS_ISA redefinition to match the change made for the generic MIPSr1 CPUs by commit 344ebf09 ("MIPS: Always use -march=<arch>, not -<arch> shortcuts").] Signed-off-by:
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- 30 Jul, 2018 5 commits
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Quentin Schulz authored
The GPIO controller also serves as an interrupt controller for events on the GPIO it handles. An interrupt occurs whenever a GPIO line has changed. Signed-off-by:
Quentin Schulz <quentin.schulz@bootlin.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Paul Burton authored
Enable CONFIG_MIPS_AUTO_PFN_OFFSET for the generic platform, allowing it to avoid wasted book-keeping for pages with addresses lower than the physical base address of memory. This has a minimal impact on kernel text size, with 64r6el_defconfig gaining 0.1% in size as reported by bloat-o-meter: add/remove: 4/1 grow/shrink: 345/13 up/down: 9017/-392 (8625) Function old new delta pcpu_setup_first_chunk 1444 1780 +336 pcpu_alloc_first_chunk 864 1136 +272 start_kernel 1064 1288 +224 initcall_blacklist 224 372 +148 try_fill_recv 2088 2184 +96 ... Total: Before=8457273, After=8465898, chg +0.10% The gain for systems with large offsets to physical memory & the ability to continue using generic kernels on such systems seems well worth this small cost. Signed-off-by:
Vladimir Kondratiev <vladimir.kondratiev@intel.com> Patchwork: https://patchwork.linux-mips.org/patch/20049/ Cc: James Hogan <jhogan@kernel.org> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
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Paul Burton authored
On systems where physical memory begins at a non-zero address, defining PHYS_OFFSET (which influences ARCH_PFN_OFFSET) can save us time & memory by avoiding book-keeping for pages from address zero to the start of memory. Some MIPS platforms already make use of this, but with the definition of PHYS_OFFSET being compile-time constant it hasn't been possible to enable this optimization for a kernel which may run on systems with varying physical memory base addresses. Introduce a new Kconfig option CONFIG_MIPS_AUTO_PFN_OFFSET which, when enabled, makes ARCH_PFN_OFFSET a variable & detects it from the boot memory map (which for example may have been populated from DT). The relationship with PHYS_OFFSET is reversed, with PHYS_OFFSET now being based on ARCH_PFN_OFFSET. This is because ARCH_PFN_OFFSET is used far more often, so avoiding the need for runtime calculation gives us a smaller impact on kernel text size (0.1% rather than 0.15% for 64r6el_defconfig). Signed-off-by:
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Paul Burton authored
isa_virt_to_bus() & isa_bus_to_virt() claim to treat ISA bus addresses as being identical to physical addresses, but they fail to do so in the presence of a non-zero PHYS_OFFSET. Correct this by having them use virt_to_phys() & phys_to_virt(), which consolidates the calculations to one place & ensures that ISA bus addresses do indeed match physical addresses. Signed-off-by:
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Paul Burton authored
Converting an address between cached & uncached (typically addresses in (c)kseg0 & (c)kseg1 or 2 xkphys regions) should not depend upon PHYS_OFFSET in any way - we're converting from a virtual address in one unmapped region to a virtual address in another unmapped region. For some reason our CAC_ADDR() & UNCAC_ADDR() macros make use of PAGE_OFFSET, which typically includes PHYS_OFFSET. This means that platforms with a non-zero PHYS_OFFSET typically have to workaround miscalculation by these 2 macros by also defining UNCAC_BASE to a value that isn't really correct. It appears that an attempt has previously been made to address this with commit 3f4579252aa1 ("MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET") which was later undone by commit ed3ce16c ("Revert "MIPS: make CAC_ADDR and UNCAC_ADDR account for PHYS_OFFSET"") which also introduced the ar7 workaround. That attempt at a fix was roughly equivalent, but essentially caused the CAC_ADDR() & UNCAC_ADDR() macros to cancel out PHYS_OFFSET by adding & then subtracting it again. In his revert Leonid is correct that using PHYS_OFFSET makes no sense in the context of these macros, but appears to have missed its inclusion via PAGE_OFFSET which means PHYS_OFFSET actually had an effect after the revert rather than before it. Here we fix this by modifying CAC_ADDR() & UNCAC_ADDR() to stop using PAGE_OFFSET (& thus PHYS_OFFSET), instead using __pa() & __va() along with UNCAC_BASE. For UNCAC_ADDR(), __pa() will convert a cached address to a physical address which we can simply use as an offset from UNCAC_BASE to obtain an address in the uncached region. For CAC_ADDR() we can undo the effect of UNCAC_ADDR() by subtracting UNCAC_BASE and using __va() on the result. With this change made, remove definitions of UNCAC_BASE from the ar7 & pic32 platforms which appear to have defined them only to workaround this problem. Signed-off-by:
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- 28 Jul, 2018 4 commits
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Nicholas Mc Guire authored
of_find_compatible_node() returns a device_node pointer with refcount incremented and must be decremented explicitly. As this code is using the result only to check presence of the interrupt controller (!NULL) but not actually using the result otherwise the refcount can be decremented here immediately again. Signed-off-by:
Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by:
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Nicholas Mc Guire authored
The call to of_find_node_by_name returns a node pointer with refcount incremented thus it must be explicitly decremented here after the last usage. Signed-off-by:
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Paul Burton authored
VDSO code should not be using smp_processor_id(), since it is executed in user mode. Introduce a VDSO-specific path which will cause a compile-time or link-time error (depending upon support for __compiletime_error) if the VDSO ever incorrectly attempts to use smp_processor_id(). [Matt Redfearn <matt.redfearn@imgtec.com>: Move before change to smp_processor_id in series] Signed-off-by:
Matt Redfearn <matt.redfearn@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/17932/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <jhogan@kernel.org> Cc: linux-mips@linux-mips.org
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Alban Bedel authored
Now that the GPIO driver support interrupts we don't need to poll the buttons. Signed-off-by:
Alban Bedel <albeu@free.fr> Signed-off-by:
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- 27 Jul, 2018 1 commit
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Christoph Hellwig authored
mips_swiotlb_ops differs from the generic swiotlb_dma_ops only in that it contains a mb() barrier after each operations that maps or syncs dma memory to the device. The dma operations are defined to not be memory barriers, but instead the write* operations to kick the DMA off are supposed to contain them. For mips this handled by war_io_reorder_wmb(), which evaluates to the stronger wmb() instead of the pure compiler barrier barrier() for just those platforms that use swiotlb, so I think we are covered properly. [paul.burton@mips.com: - Include linux/swiotlb.h to fix build failures for configs with CONFIG_SWIOTLB=y.] Signed-off-by:Christoph Hellwig <hch@lst.de> Signed-off-by:
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- 26 Jul, 2018 5 commits
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Paul Burton authored
If a driver causes DMA cache maintenance with a zero length then we currently BUG and kill the kernel. As this is a scenario that we may well be able to recover from, WARN & return in the condition instead. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/14623/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org
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Alban Bedel authored
The binding for the USB PHY went thru before the driver. However the new version of the driver now use the PHY core support for reset, and this expect the reset to be named "phy". So remove the "usb-" prefix from the the reset names. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Quentin Schulz authored
There is an additional MIIM (MDIO) bus in this SoC so let's declare it in the dtsi. This bus requires GPIO 14 and 15 pins that need to be muxed. There is no support for internal PHY reset on this bus on the contrary of MIIM0 so there is only one register address space and not two. Signed-off-by:
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Quentin Schulz authored
The length of memory address space for MIIM0 is from 0x7107009c to 0x710700bf included which is 36 bytes long in decimal, or 0x24 bytes in hexadecimal and not 0x36. Fixes: 49b03169 ("MIPS: mscc: Add switch to ocelot") Signed-off-by:
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Alexandre Belloni authored
The RTC definitions were moved to the driver, remove them from the platform header. [paul.burton@mips.com: - Also remove the unused tx4939_rtcptr which would use struct tx4939_rtc_reg if it were ever expanded.] Signed-off-by:
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- 25 Jul, 2018 11 commits
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Mathias Kresin authored
The ar724x pci driver expects the PCIe controller to be brought out of reset by the bootloader. At least the AVM Fritz 300E bootloader doesn't take care of releasing the different PCIe controller related resets which causes an endless hang as soon as either the PCIE Reset register (0x180f0018) or the PCI Application Control register (0x180f0000) is read from. Do the full "PCIE Root Complex Initialization Sequence" if the PCIe host controller is still in reset during probing. The QCA u-boot sleeps 10ms after the PCIE Application Control bit is set to ready. It has been shown that 10ms might not be enough time if PCIe should be used right after setting the bit. During my tests it took up to 20ms till the link was up. Giving the link up to 100ms should work for all cases. Signed-off-by:
Mathias Kresin <dev@kresin.me> Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
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Gabor Juhos authored
This patch ensures, that the pinmux register is properly setup for the boot console UART when early_printk is enabled. [paul.burton@mips.com: - s/poinmux/pinmux/ - s/uart/UART/ - Drop extraneous parentheses.] Signed-off-by:
Gabor Juhos <juhosg@openwrt.org> Signed-off-by:
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Felix Fietkau authored
This patch adds a few additional cpu feature overrides so that they do not need to be probed at runtime. Signed-off-by:
Felix Fietkau <nbd@nbd.name> Signed-off-by:
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Felix Fietkau authored
This patch disables irq on reboot to fix hang issues that were observed due to pending interrupts. Signed-off-by:
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John Crispin authored
The pinmux on QCA SoCs is controlled by a single register. The "pinctrl-single" driver can be used but requires the target to select PINCTRL. Signed-off-by:
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Matthias Schiffer authored
This patch adds support for 2 new types of QCA silicon. TP9343 is essentially the same as the QCA956X but is licensed by TPLink. Signed-off-by:
Weijie Gao <hackpascal@gmail.com> Signed-off-by:
Matthias Schiffer <mschiffer@universe-factory.net> Signed-off-by:
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Gabor Juhos authored
This patch adds many new registers for various QCA MIPS SoCs. The patch is an aggragate of many contributions made to OpenWrt. Signed-off-by:
Henryk Heisig <hyniu@o2.pl> Signed-off-by:
Julien Dusser <julien.dusser@free.fr> Signed-off-by:
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Alexandre Belloni authored
Ocelot now has a u-boot port, allow building FIT images instead of relying on the legacy detection and builtin DTB. Signed-off-by:
James Hogan <jhogan@kernel.org> Signed-off-by:
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Steven J. Hill authored
Get rid of extern declarations in .c functions and included the necessary header file. Also remove unused UART declares. Signed-off-by:
Steven J. Hill <steven.hill@cavium.com> Signed-off-by:
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Matt Redfearn authored
It is not immediately obvious what the expected inputs to these fault handlers is and how they calculate the number of unset bytes. Having stared deeply at this in order to fix some corner cases, add some comments to assist those who follow. Signed-off-by:
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Matt Redfearn authored
The __clear_user function is defined to return the number of bytes that could not be cleared. From the underlying memset / bzero implementation this means setting register a2 to that number on return. Currently if a page fault is triggered within the MIPSr6 version of setting of initial unaligned bytes, the value loaded into a2 on return is meaningless. During the MIPSr6 version of the initial unaligned bytes block, register a2 contains the number of bytes to be set beyond the initial unaligned bytes. The t0 register is initally set to the number of unaligned bytes - STORSIZE, effectively a negative version of the number of unaligned bytes. This is then incremented before each byte is saved. The label .Lbyte_fixup\@ is jumped to on page fault. Currently the value in a2 is incorrectly replaced by 0 - t0 + 1, effectively the number of unaligned bytes remaining. This leads to the failures being reported by the following test code: static int __init test_clear_user(void) { int j, k; pr_info("\n\n\nTesting clear_user\n"); for (j = 0; j < 512; j++) { if ((k = clear_user(NULL+3, j)) != j) { pr_err("clear_user (NULL %d) returned %d\n", j, k); } } return 0; } late_initcall(test_clear_user); Which reports: [ 3.965439] Testing clear_user [ 3.973169] clear_user (NULL 8) returned 6 [ 3.976782] clear_user (NULL 9) returned 6 [ 3.980390] clear_user (NULL 10) returned 6 [ 3.984052] clear_user (NULL 11) returned 6 [ 3.987524] clear_user (NULL 12) returned 6 Fix this by subtracting t0 from a2 (rather than $0), effectivey giving: unset_bytes = (#bytes - (#unaligned bytes)) - (-#unaligned bytes remaining + 1) + 1 a2 = a2 - t0 + 1 This fixes the value returned from __clear user when the number of bytes to set is > LONGSIZE and the address is invalid and unaligned. Unfortunately, this breaks the fixup handling for unaligned bytes after the final long, where register a2 still contains the number of bytes remaining to be set and the t0 register is to 0 - the number of unaligned bytes remaining. Because t0 is now is now subtracted from a2 rather than 0, the number of bytes unset is reported incorrectly: static int __init test_clear_user(void) { char *test; int j, k; pr_info("\n\n\nTesting clear_user\n"); test = vmalloc(PAGE_SIZE); for (j = 256; j < 512; j++) { if ((k = clear_user(test + PAGE_SIZE - 254, j)) != j - 254) { pr_err("clear_user (%px %d) returned %d\n", test + PAGE_SIZE - 254, j, k); } } return 0; } late_initcall(test_clear_user); [ 3.976775] clear_user (c00000000000df02 256) returned 4 [ 3.981957] clear_user (c00000000000df02 257) returned 6 [ 3.986425] clear_user (c00000000000df02 258) returned 8 [ 3.990850] clear_user (c00000000000df02 259) returned 10 [ 3.995332] clear_user (c00000000000df02 260) returned 12 [ 3.999815] clear_user (c00000000000df02 261) returned 14 Fix this by ensuring that a2 is set to 0 during the set of final unaligned bytes. Signed-off-by:
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