- 31 Oct, 2020 40 commits
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Karsten Graul authored
To allow better problem diagnosis the return codes for SMC-Dv2 are improved by this patch. A few more CLC DECLINE codes are defined and sent to the peer when an SMC connection cannot be established. There are now multiple SMC variations that are offered by the client and the server may encounter problems to initialize all of them. Because only one diagnosis code can be sent to the client the decision was made to send the first code that was encountered. Because the server tries the variations in the order of importance (SMC-Dv2, SMC-D, SMC-R) this makes sure that the diagnosis code of the most important variation is sent. v2: initialize rc in smc_listen_v2_check(). Signed-off-by:
Karsten Graul <kgraul@linux.ibm.com> Link: https://lore.kernel.org/r/20201031181938.69903-1-kgraul@linux.ibm.comSigned-off-by:
Jakub Kicinski <kuba@kernel.org>
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Jakub Kicinski authored
Subbaraya Sundeep says: ==================== Support for OcteonTx2 98xx silicon OcteonTx2 series of silicons have multiple variants, the 98xx variant has two network interface controllers (NIX blocks) each of which supports upto 100Gbps. Similarly 98xx supports two crypto blocks (CPT) to double the crypto performance. The current RVU drivers support a single NIX and CPT blocks, this patchset adds support for multiple blocks of same type to be active at the same time. Also the number of serdes controllers (CGX) have increased from three to five on 98xx. Each of the CGX block supports upto 4 physical interfaces depending on the serdes mode ie upto 20 physical interfaces. At a time each CGX block can be mapped to a single NIX. The HW configuration to map CGX and NIX blocks is done by firmware. NPC has two new interfaces added NIX1_RX and NIX1_TX similar to NIX0 interfaces. Also MCAM entries is increased from 4k to 16k. To support the 16k entries extended set is added in hardware which are at completely different register offsets. Fortunately new constant registers can be read to figure out the extended set is present or not. This patch set modifies existing AF and PF drivers in below order to support 98xx: - Prepare for supporting multiple blocks of same type. Functions which operate with block type to get or set resources count are modified to operate with block address - Manage allocating and freeing LFs from new NIX1 and CPT1 RVU blocks. - NIX block specific initialization and teardown for NIX1 - Based on the mapping set by Firmware, assign the NIX block LFs to a PF/VF. - Multicast entries context is setup for NIX1 along with NIX0 - NPC changes to support extended set of MCAM entries, counters and NIX1 interfaces to NPC. - All the mailbox changes required for the new blocks in 98xx. - Since there are more CGX links in 98xx the hardcoded LBK link value needed by netdev drivers is not sufficient any more. Hence AF consumers need to get the number of all links and calculate the LBK link. - Debugfs changes to display NIX1 contexts similar to NIX0 - Debugfs change to display mapping between CGX, NIX and PF. ==================== Link: https://lore.kernel.org/r/1603948549-781-1-git-send-email-sundeep.lkml@gmail.comSigned-off-by:
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Rakesh Babu authored
Unlike earlier silicon variants, OcteonTx2 98xx silicon has 2 NIX blocks and each of the CGX is mapped to either of the NIX blocks. Each NIX block supports 100G. Mapping btw NIX blocks and CGX is done by firmware based on CGX speed config to have a maximum possible network bandwidth. Since the mapping is not fixed, it's difficult for a user to figure out. Hence added a debugfs entry which displays mapping between CGX LMAC, NIX block and RVU PF. Sample result of this entry :: ~# cat /sys/kernel/debug/octeontx2/rvu_pf_cgx_map PCI dev RVU PF Func NIX block CGX LMAC 0002:02:00.0 0x400 NIX0 CGX0 LMAC0 Signed-off-by:
Rakesh Babu <rsaladi2@marvell.com> Signed-off-by:
Sunil Goutham <sgoutham@marvell.com> Signed-off-by:
Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by:
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Rakesh Babu authored
If NIX1 block is also implemented then add a new directory for NIX1 in debugfs root. Stats of NIX1 block can be read/writen from/to the files in directory "/sys/kernel/debug/octeontx2/nix1/". Signed-off-by:
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Subbaraya Sundeep authored
CGX links are followed by LBK links but number of CGX and LBK links varies between platforms. Hence get the number of links present in hardware from AF and use it to calculate LBK link number. Signed-off-by:
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Subbaraya Sundeep authored
This patch puts together all mailbox changes for 98xx silicon: Attach -> Modify resource attach mailbox handler to request LFs from a block address out of multiple blocks of same type. If a PF/VF need LFs from two blocks of same type then attach mbox should be called twice. Example: struct rsrc_attach *attach; .. Allocate memory for message .. attach->cptlfs = 3; /* 3 LFs from CPT0 */ .. Send message .. .. Allocate memory for message .. attach->modify = 1; attach->cpt_blkaddr = BLKADDR_CPT1; attach->cptlfs = 2; /* 2 LFs from CPT1 */ .. Send message .. Detach -> Update detach mailbox and its handler to detach resources from CPT1 and NIX1 blocks. MSIX -> Updated the MSIX mailbox and its handler to return MSIX offsets for the new block CPT1. Free resources -> Update free_rsrc mailbox and its handler to return the free resources count of new blocks NIX1 and CPT1 Links -> Number of CGX,LBK and SDP links may vary between platforms. For example, in 98xx number of CGX and LBK links are more than 96xx. Hence the info about number of links present in hardware is useful for consumers to request link configuration properly. This patch sends this info in nix_lf_alloc_rsp. Signed-off-by: -
Subbaraya Sundeep authored
On 98xx silicon, NPC block has additional mcam entries, counters and NIX1 interfaces. Extended set of registers are present for the new mcam entries and counters. This patch does the following: - updates the register accessing macros to use extended set if present. - configures the MKEX profile for NIX1 interfaces also. - updates mcam entry write functions to use assigned NIX0/1 interfaces for the PF/VF. Signed-off-by:
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Subbaraya Sundeep authored
Initialize MCE context for the assigned NIX0/1 block for a CGX mapped PF. Modified rvu_nix_aq_enq_inst function to work with nix_hw so that MCE contexts for both NIX blocks can be inited. Signed-off-by:
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Subbaraya Sundeep authored
Firmware configures NIX block mapping for all CGXs to achieve maximum throughput. This patch reads the configuration and create mapping between RVU PF and NIX blocks. And for LBK VFs assign NIX0 for even numbered VFs and NIX1 for odd numbered VFs. Signed-off-by:
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Rakesh Babu authored
This patch modifies NIX functions to operate with nix_hw context so that existing functions can be used for both NIX0 and NIX1 blocks. And the NIX blocks present in the system are initialized during driver init and freed during exit. Signed-off-by:
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Rakesh Babu authored
AF manages the tasks of allocating, freeing LFs from RVU blocks to PF and VFs. With new NIX1 and CPT1 blocks in 98xx, this patch adds support for handling new blocks too. Co-developed-by:
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Subbaraya Sundeep authored
Since multiple blocks of same type are present in 98xx, modify functions which get resource count and which update resource count to work with individual block address instead of block type. Reviewed-by:
Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by:
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Robert Hancock authored
Update the axienet driver to properly support the Xilinx PCS/PMA PHY component which is used for 1000BaseX and SGMII modes, including properly configuring the auto-negotiation mode of the PHY and reading the negotiated state from the PHY. Signed-off-by:
Robert Hancock <robert.hancock@calian.com> Reviewed-by:
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/20201028171429.1699922-1-robert.hancock@calian.comSigned-off-by:
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Alex Elder authored
The previous commit added support for IPA having up to six source and destination resources. But currently nothing uses more than four. (Five of each are used in a newer version of the hardware.) I find that in one of my build environments the compiler complains about newly-added code in two spots. Inspection shows that the warnings have no merit, but this compiler does not recognize that. ipa_main.c:457:39: warning: array index 5 is past the end of the array (which contains 4 elements) [-Warray-bounds] (and the same warning at line 483) We can make this warning go away by changing the number of elements in the source and destination resource limit arrays--now rather than waiting until we need it to support the newer hardware. This change was coming soon anyway; make it now to get rid of the warning. Signed-off-by:Alex Elder <elder@linaro.org> Link: https://lore.kernel.org/r/20201031151524.32132-1-elder@linaro.orgSigned-off-by:
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Jakub Kicinski authored
Heiner Kallweit says: ==================== net: add functionality to net core byte/packet counters and use it in r8169 This series adds missing functionality to the net core handling of byte/packet counters and statistics. The extensions are then used to remove private rx/tx byte/packet counters in r8169 driver. ==================== Link: https://lore.kernel.org/r/1fdb8ecd-be0a-755d-1d92-c62ed8399e77@gmail.comSigned-off-by:
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Heiner Kallweit authored
After switching to the net core rx/tx byte/packet counters we can remove the now unused private version. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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Heiner Kallweit authored
Switch to the net core rx/tx byte/packet counter infrastructure. This simplifies the code, only small drawback is some memory overhead because we use just one queue, but allocate the counters per cpu. Signed-off-by:
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Heiner Kallweit authored
We have netdev_alloc_pcpu_stats(), and we have devm_alloc_percpu(). Add a managed version of netdev_alloc_pcpu_stats, e.g. for allocating the per-cpu stats in the probe() callback of a driver. It needs to be a macro for dealing properly with the type argument. Signed-off-by:
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Heiner Kallweit authored
Add dev_sw_netstats_tx_add(), complementing already existing dev_sw_netstats_rx_add(). Other than dev_sw_netstats_rx_add allow to pass the number of packets as function argument. Signed-off-by:
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Jakub Kicinski authored
Sebastian Andrzej Siewior says: ==================== in_interrupt() cleanup, part 2 in the discussion about preempt count consistency across kernel configurations: https://lore.kernel.org/r/20200914204209.256266093@linutronix.de/ Linus clearly requested that code in drivers and libraries which changes behaviour based on execution context should either be split up so that e.g. task context invocations and BH invocations have different interfaces or if that's not possible the context information has to be provided by the caller which knows in which context it is executing. This includes conditional locking, allocation mode (GFP_*) decisions and avoidance of code paths which might sleep. In the long run, usage of 'preemptible, in_*irq etc.' should be banned from driver code completely. This is part two addressing remaining drivers except for orinoco-usb. ==================== Cherry picking only Ethernet changes. Link: https://lore.kernel.org/r/20201027225454.3492351-1-bigeasy@linutronix.deSigned-off-by:
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Sebastian Andrzej Siewior authored
The driver uses in_irq() to determine if the tlan_priv::lock has to be acquired in tlan_mii_read_reg() and tlan_mii_write_reg(). The interrupt handler acquires the lock outside of these functions so the in_irq() check is meant to prevent a lock recursion deadlock. But this check is incorrect when interrupt force threading is enabled because then the handler runs in thread context and in_irq() correctly returns false. The usage of in_*() in drivers is phased out and Linus clearly requested that code which changes behaviour depending on context should either be seperated or the context be conveyed in an argument passed by the caller, which usually knows the context. tlan_set_timer() has this conditional as well, but this function is only invoked from task context or the timer callback itself. So it always has to lock and the check can be removed. tlan_mii_read_reg(), tlan_mii_write_reg() and tlan_phy_print() are invoked from interrupt and other contexts. Split out the actual function body into helper variants which are called from interrupt context and make the original functions wrappers which acquire tlan_priv::lock unconditionally. Signed-off-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Cc: Samuel Chessman <chessman@tux.org> Signed-off-by:
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Sebastian Andrzej Siewior authored
nv_update_stats() triggers a WARN_ON() when invoked from hard interrupt context because the locks in use are not hard interrupt safe. It also has an assert_spin_locked() which was the lock check before the lockdep era. Lockdep has way broader locking correctness checks and covers both issues, so replace the warning and the lock assert with lockdep_assert_held(). Signed-off-by:
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Sebastian Andrzej Siewior authored
wait_for_cmd_complete() uses in_interrupt() to detect whether it is safe to sleep or not. The usage of in_interrupt() in drivers is phased out and Linus clearly requested that code which changes behaviour depending on context should either be seperated or the context be conveyed in an argument passed by the caller, which usually knows the context. in_interrupt() also is only partially correct because it fails to chose the correct code path when just preemption or interrupts are disabled. Add an argument 'may_block' to both functions and adjust the callers to pass the context information. The following call chains which end up invoking wait_for_cmd_complete() were analyzed to be safe to sleep: s2io_card_up() s2io_set_multicast() init_nic() init_tti() s2io_close() do_s2io_delete_unicast_mc() do_s2io_add_mac() s2io_set_mac_addr() do_s2io_prog_unicast() do_s2io_add_mac() s2io_reset() do_s2io_restore_unicast_mc() do_s2io_add_mc() do_s2io_add_mac() s2io_open() do_s2io_prog_unicast() do_s2io_add_mac() The following call chains which end up invoking wait_for_cmd_complete() were analyzed to be safe to sleep: __dev_set_rx_mode() s2io_set_multicast() s2io_txpic_intr_handle() s2io_link() init_tti() Add a may_sleep argument to wait_for_cmd_complete(), s2io_set_multicast() and init_tti() and hand the context information in from the call sites. Signed-off-by: -
Jakub Kicinski authored
Vladimir Oltean says: ==================== L2 multicast forwarding for Ocelot switch This series enables the mscc_ocelot switch to forward raw L2 (non-IP) mdb entries as configured by the bridge driver after this patch: https://patchwork.ozlabs.org/project/netdev/patch/20201028233831.610076-1-vladimir.oltean@nxp.com/ ==================== Link: https://lore.kernel.org/r/20201029022738.722794-1-vladimir.oltean@nxp.comSigned-off-by:
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Vladimir Oltean authored
There is one main difference in mscc_ocelot between IP multicast and L2 multicast. With IP multicast, destination ports are encoded into the upper bytes of the multicast MAC address. Example: to deliver the address 01:00:5E:11:22:33 to ports 3, 8, and 9, one would need to program the address of 00:03:08:11:22:33 into hardware. Whereas for L2 multicast, the MAC table entry points to a Port Group ID (PGID), and that PGID contains the port mask that the packet will be forwarded to. As to why it is this way, no clue. My guess is that not all port combinations can be supported simultaneously with the limited number of PGIDs, and this was somehow an issue for IP multicast but not for L2 multicast. Anyway. Prior to this change, the raw L2 multicast code was bogus, due to the fact that there wasn't really any way to test it using the bridge code. There were 2 issues: - A multicast PGID was allocated for each MDB entry, but it wasn't in fact programmed to hardware. It was dummy. - In fact we don't want to reserve a multicast PGID for every single MDB entry. That would be odd because we can only have ~60 PGIDs, but thousands of MDB entries. So instead, we want to reserve a multicast PGID for every single port combination for multicast traffic. And since we can have 2 (or more) MDB entries delivered to the same port group (and therefore PGID), we need to reference-count the PGIDs. Signed-off-by:
Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
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Vladimir Oltean authored
This saves a re-classification of the MDB address on deletion. Signed-off-by:
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Vladimir Oltean authored
It is Not Needed, a comment will suffice. Signed-off-by:
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Vladimir Oltean authored
Since a helper is available for copying Ethernet addresses, let's use it. Signed-off-by:
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Vladimir Oltean authored
ocelot.h says: /* MAC table entry types. * ENTRYTYPE_NORMAL is subject to aging. * ENTRYTYPE_LOCKED is not subject to aging. * ENTRYTYPE_MACv4 is not subject to aging. For IPv4 multicast. * ENTRYTYPE_MACv6 is not subject to aging. For IPv6 multicast. */ We don't want the permanent entries added with 'bridge mdb' to be subject to aging. Signed-off-by:
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Vladimir Oltean authored
When creating a new multicast port group, there is implicit conversion between the __u8 state member of struct br_mdb_entry and the unsigned char flags member of struct net_bridge_port_group. This implicit conversion relies on the fact that MDB_PERMANENT is equal to MDB_PG_FLAGS_PERMANENT. Let's be more explicit and convert the state to flags manually. Signed-off-by:
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Nikolay Aleksandrov authored
Extend the bridge multicast control and data path to configure routes for L2 (non-IP) multicast groups. The uapi struct br_mdb_entry union u is extended with another variant, mac_addr, which does not change the structure size, and which is valid when the proto field is zero. To be compatible with the forwarding code that is already in place, which acts as an IGMP/MLD snooping bridge with querier capabilities, we need to declare that for L2 MDB entries (for which there exists no such thing as IGMP/MLD snooping/querying), that there is always a querier. Otherwise, these entries would be flooded to all bridge ports and not just to those that are members of the L2 multicast group. Needless to say, only permanent L2 multicast groups can be installed on a bridge port. Signed-off-by:
Nikolay Aleksandrov <nikolay@nvidia.com> Signed-off-by:
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Jakub Kicinski authored
Edward Cree says: ==================== sfc: EF100 TSO enhancements Support TSO over encapsulation (with GSO_PARTIAL), and over VLANs (which the code already handled but we didn't advertise). Also correct our handling of IPID mangling. I couldn't find documentation of exactly what shaped SKBs we can get given, so patch #2 is slightly guesswork, but when I tested TSO over both underlay and (VxLAN) overlay, the checksums came out correctly, so at least in those cases the edits we're making must be the right ones. Similarly, I'm not 100% sure I've correctly understood how FIXEDID and MANGLEID are supposed to work in patch #3. ==================== Link: https://lore.kernel.org/r/6e1ea05f-faeb-18df-91ef-572445691d89@solarflare.comSigned-off-by:
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Edward Cree authored
Signed-off-by:
Edward Cree <ecree@solarflare.com> Signed-off-by:
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Edward Cree authored
AIUI, the NETIF_F_TSO_MANGLEID flag is a signal to the stack that a driver may _need_ to mangle IDs in order to do TSO, and conversely a signal from the stack that the driver is permitted to do so. Since we support both fixed and incrementing IPIDs, we should rely on the SKB_GSO_FIXEDID flag on a per-skb basis, rather than using the MANGLEID feature to make all TSOs fixed-id. Includes other minor cleanups of ef100_make_tso_desc() coding style. Signed-off-by:
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Edward Cree authored
The NIC only needs to know where the headers it has to edit (TCP and inner and outer IPv4) are, which fits GSO_PARTIAL nicely. It also supports non-PARTIAL offload of UDP tunnels, again just needing to be told the outer transport offset so that it can edit the UDP length field. (It's not clear to me whether the stack will ever use the non-PARTIAL version with the netdev feature flags we're setting here.) Signed-off-by:
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Edward Cree authored
We need EFX_POPULATE_OWORD_17 for an encap TSO descriptor on EF100. Signed-off-by:
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Jakub Kicinski authored
Alex Elder says: ==================== net: ipa: minor bug fixes This series fixes several bugs. They are minor, in that the code currently works on supported platforms even without these patches applied, but they're bugs nevertheless and should be fixed. Version 2 improves the commit message for the fourth patch. It also fixes a bug in two spots in the last patch. Both of these changes were suggested by Willem de Bruijn. ==================== Link: https://lore.kernel.org/r/20201028194148.6659-1-elder@linaro.orgSigned-off-by:
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Alex Elder authored
The minimum and maximum limits for resources assigned to a given resource group are programmed in pairs, with the limits for two groups set in a single register. If the number of supported resource groups is odd, only half of the register that defines these limits is valid for the last group; that group has no second group in the pair. Currently we ignore this constraint, and it turns out to be harmless, but it is not guaranteed to be. This patch addresses that, and adds support for programming the 5th resource group's limits. Rework how the resource group limit registers are programmed by having a single function program all group pairs rather than having one function program each pair. Add the programming of the 4-5 resource group pair limits to this function. If a resource group is not supported, pass a null pointer to ipa_resource_config_common() for that group and have that function write zeroes in that case. Tested-by:
Sujit Kautkar <sujitka@chromium.org> Signed-off-by:
Willem de Bruijn <willemb@google.com> Signed-off-by:
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Alex Elder authored
The number of resource groups supported by the hardware can be different for source and destination resources. Determine the number supported for each using separate functions. Make the functions inline end move their definitions into "ipa_reg.h", because they determine whether certain register definitions are valid. Pass just the IPA hardware version as argument. IPA_RESOURCE_GROUP_COUNT represents the maximum number of resource groups the driver supports for any hardware version. Change that symbol to be two separate constants, one for source and the other for destination resource groups. Rename them to end with "_MAX" rather than "_COUNT", to reflect their true purpose. Tested-by:
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Alex Elder authored
The IPA hardware manages various resources (e.g. descriptors) internally to perform its functions. The resources are grouped, allowing different endpoints to use separate resource pools. This way one group of endpoints can be configured to operate unaffected by the resource use of endpoints in a different group. Endpoints should be assigned to a resource group, but we currently don't do that. Define a new resource_group field in the endpoint configuration data, and use it to assign the proper resource group to use for each AP endpoint. Tested-by:
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