1. 20 Jun, 2016 25 commits
  2. 16 Jun, 2016 5 commits
  3. 15 Jun, 2016 10 commits
    • Paolo Bonzini's avatar
      KVM: remove kvm_vcpu_compatible · 557abc40
      Paolo Bonzini authored
      The new created_vcpus field makes it possible to avoid the race between
      irqchip and VCPU creation in a much nicer way; just check under kvm->lock
      whether a VCPU has already been created.
      
      We can then remove KVM_APIC_ARCHITECTURE too, because at this point the
      symbol is only governing the default definition of kvm_vcpu_compatible.
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      557abc40
    • Paolo Bonzini's avatar
      KVM: introduce kvm->created_vcpus · 6c7caebc
      Paolo Bonzini authored
      The race between creating the irqchip and the first VCPU is
      currently fixed by checking the presence of an irqchip before
      updating kvm->online_vcpus, and undoing the whole VCPU creation
      if someone created the irqchip in the meanwhile.
      
      Instead, introduce a new field in struct kvm that will count VCPUs
      under a mutex, without the atomic access and memory ordering that we
      need elsewhere to protect the vcpus array.  This also plugs the race
      and is more easily applicable in all similar circumstances.
      Reviewed-by: default avatarCornelia Huck <cornelia.huck@de.ibm.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      6c7caebc
    • Borislav Petkov's avatar
      x86/kvm/svm: Simplify cpu_has_svm() · 682a8108
      Borislav Petkov authored
      Use already cached CPUID information instead of querying CPUID again.
      
      No functionality change.
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Cc: Joerg Roedel <joro@8bytes.org>
      Cc: kvm@vger.kernel.org
      Cc: x86@kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      682a8108
    • James Hogan's avatar
      MIPS: KVM: Use mipsregs.h defs for config registers · 4e10b764
      James Hogan authored
      Convert MIPS KVM guest register state initialisation to use the standard
      <asm/mipsregs.h> register field definitions for Config registers, and
      drop the custom definitions in kvm_host.h which it was using before.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      4e10b764
    • James Hogan's avatar
      MIPS: KVM: Report more accurate CP0_Config fields to guest · e342925f
      James Hogan authored
      Initialise the guest's CP0_Config register with a few more bits of
      information from the host. The BE bit should be set on big endian
      machines, the VI bit should be set on machines with a virtually tagged
      instruction cache, and the reported architecture revision should match
      that of the host (since we won't support emulating pre-r6 instruction
      encodings on r6 or vice versa).
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      e342925f
    • James Hogan's avatar
      MIPS: Add define for Config.VI (virtual icache) bit · 4b34bca0
      James Hogan authored
      The Config.VI bit specifies that the instruction cache is virtually
      tagged, which is checked in c-r4k.c's probe_pcache(). Add a proper
      definition for it in mipsregs.h and make use of it.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      4b34bca0
    • James Hogan's avatar
      MIPS: KVM: Use host CCA for TLB mappings · 7414d2f6
      James Hogan authored
      KVM TLB mappings for the guest were being created with a cache coherency
      attribute (CCA) of 3, which is cached incoherent. Create them instead
      with the default host CCA, which should be the correct one for coherency
      on SMP systems.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      7414d2f6
    • James Hogan's avatar
      MIPS: KVM: Move commpage so 0x0 is unmapped · 42aa12e7
      James Hogan authored
      The comm page which is mapped into the guest kernel address space at
      0x0 has the unfortunate side effect of allowing guest kernel NULL
      pointer dereferences to succeed. The only constraint on this address is
      that it must be within 32KiB of 0x0, so that single lw/sw instructions
      (which have 16-bit signed offset fields) can be used to access it, using
      the zero register as a base.
      
      So lets move the comm page as high as possible within that constraint so
      that 0x0 can be left unmapped, at least for page sizes < 32KiB.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      42aa12e7
    • James Hogan's avatar
      MIPS: KVM: Add KScratch registers · 05108709
      James Hogan authored
      Allow up to 6 KVM guest KScratch registers to be enabled and accessed
      via the KVM guest register API and from the guest itself (the fallback
      reading and writing of commpage registers is sufficient for KScratch
      registers to work as expected).
      
      User mode can expose the registers by setting the appropriate bits of
      the guest Config4.KScrExist field. KScratch registers that aren't usable
      won't be writeable via the KVM Ioctl API.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      05108709
    • James Hogan's avatar
      MIPS: KVM: Emulate RDHWR CPUNum register · cf1fb0f2
      James Hogan authored
      Actually provide the VCPU number when emulating the RDHWR CPUNum
      register, so that it will match the CPUNum field of CP0_EBase register,
      rather than always returning 0.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Radim Krčmář <rkrcmar@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      cf1fb0f2