- 08 Nov, 2013 40 commits
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Daniel Vetter authored
HW engineers have listened and given us again a real interrupt with masking and status regs. Yay! For consistency with other platforms call the #define FIFO_UNDERRUN. Eventually we also might need to have some enable/disable functions for bdw display interrupts, but for now open-coding seems to be good enough. Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
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Daniel Vetter authored
Let's cache the IMR value like on other platforms. This is needed to implement the underrun reporting since then we'll have two places that change the same register at runtime. Reviewed-by:
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Daniel Vetter authored
The layout of the CRC registers is the same as on hsw, only the interrupt handling has changed a bit. So trivial to wire up, yay! Reviewed-by:
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Daniel Vetter authored
Gives us hotplug, gmbus, dp aux and south errors (underrun reporting!). Reviewed-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
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Daniel Vetter authored
Useful for dp aux to work better. Also stop enabling the port A hotplug event - eDP panels are expected to fire that interupt and we're not really ready to deal with them. This is consistent with how we handle port A on ilk-hsw. The more important bit is that we must delay the enabling of hotplug interrupts until all the encoders are fully set up. But we need irq support earlier than that, hence hotplug interrupts can only be enabled in the ->hpd_irq_setup callback. v2: Drop the _HOTPLUG, it isn't (Ville). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
- Pipe underrun can't just be enabled, we need some support code like on ilk-hsw to make this happen. So drop it for now. - CRC error is a special mode of the CRC hardware that we don't use, so again drop it. Real CRC support for bdw will be added later. - All the other error bits are about faults, so rename the #define and adjust the output. v2: Use pipe_name as pointed out by Ville. Ville's comment was on a previous patch, but it was easier to squash in here. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Daniel Vetter authored
We have a per-pipe bit in the master irq control register, so use it. This allows us to drop the masks for aggregate interrupt bits and be a bit more explicit in the code. It also removes one indentation level. Reviewed-by:
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Daniel Vetter authored
The handling of the error interrupts isn't wired up at all. And it hasn't been ever since ilk happened, so don't bother. Reviewed-by:
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Ben Widawsky authored
Early platforms use the same PCH as HSW, and to avoid triggering the !ULT, and !HSW warnings, simply put it first in the search. Signed-off-by:
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Ville Syrjälä authored
Broadwell should also use hsw_crt_get_config(). Just move the function pointer assignment to the if HAS_DDI block we already have there. Signed-off-by:
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Ben Widawsky authored
Cc: Art Runyan <arthur.j.runyan@intel.com> Signed-off-by:
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Ville Syrjälä authored
Like on HSW, trickle feed should always be enabled on BDW. Signed-off-by:
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Ben Widawsky authored
Implement WaSingleSubspanDispatchOnAALinesAndPoints BDW-A workaround. Signed-off-by:
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Ben Widawsky authored
Hold vertex data in cache until last reference BDW-A workaround Signed-off-by:
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Ben Widawsky authored
BDW-A workaround BDW Bug #1899155 Signed-off-by:
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Ben Widawsky authored
BDW-A workaround. BDW Bug #1899812 Signed-off-by:
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Ben Widawsky authored
BDW-A workaround BDW Bug #1899532 v2: WARN on when not using preliminary HW support Signed-off-by:
Jesse Barnes <jbarnes@virtuosugeek.org> Signed-off-by:
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Ben Widawsky authored
Signed-off-by:
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Ben Widawsky authored
This implements a workaround for PSR dealing with some vblank issue. WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD v2: forgot to git add bogus whitespace fix v3: Update with workaround names. Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville) Cc: Art Runyan <arthur.j.runyan@intel.com> Signed-off-by:
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Ben Widawsky authored
We've done insufficient testing on them thus far, so keep them disabled until we do test. v2: Use WARN when not enabling preliminary HW support as this should only be disabled for that case. v3: Rip out the now useless (and really noisy) DRM_INFO output. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ben Widawsky authored
This is mostly what we have for HSW with the exceptions of: no writes: GEN6_RC1_WAKE_RATE_LIMIT GEN6_RC6pp_WAKE_RATE_LIMIT GEN6_RC1e_THRESHOLD GEN6_RC6p_THRESHOLD GEN6_RC6pp_THRESHOLD GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s Don't try to overclock, or program ring/IA frequency tables since we don't quite have sufficient docs yet. NOTE: These values do not reflect the changes made recently by Chris. Since we have no evidence yet what the proper way to tweak for this platform is, I think it is good to go, and can be optimized by Chris, or whomever, later. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Damien Lespiau authored
Just like HSW. This means we can scan out a mode with a 300Mhz pixel clock with a depth of 24 bits, but only a 200Mhz one with a 36bits depth. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
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Ben Widawsky authored
It's no longer a required workaround on BDW. Signed-off-by:
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Ben Widawsky authored
The current formula we use for HSW is not what is in current docs. However, changing to the HSW formula on my HSW does not improve power usage, and decreases performance by about 5% in limited xonotic testing. For gen8, until we know otherwise, or run experiments, let's use the HSW formula - which should be the same used in the Windows driver (and thus help make an apples-applies comparison) on gen8. v2: Use >= 8 instead of > 7 to be consistent with all other gen checks. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: -
Ben Widawsky authored
Broadwell PSR support is a superset of Haswell. With this simple register base calculation, everything that worked on HSW for eDP PSR should work on BDW. Note that Broadwell provides additional PSR support. This is not addressed at this time. v2: Make the HAS_PSR include BDW v3: Use the correct offset (I had incorrectly used one from my faulty brain) (Art!) v4: It helps if you git add v5: Be explicit about not setting min link entry time for BDW. This should be no functional change over v4 (Jani) Reviewed-by:
Art Runyan <arthur.j.runyan@intel.com> Reviewed-by:
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Ben Widawsky authored
v2: Squash in fixup from Ben to synchronize the GT mailbox commands. CC: Art Runyan <arthur.j.runyan@intel.com> Reviewed-by:
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Ville Syrjälä authored
Broadwell has bigger display FIFOs than Haswell. Otherwise the two are very similar. v2: Fix FBC WM_LP shift for BDW v3: Rebase on top of the big Haswell wm rework. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Reviewed-by:
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Paulo Zanoni authored
Use the eDP values on platforms where port D is eDP. This doesn't affect Haswell since it uses the same DDI buffer values for eDP and DP. Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
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Paulo Zanoni authored
So treat it like Haswell. Reviewed-by:
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Paulo Zanoni authored
They're not the same as the Haswell ones. Reviewed-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
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Paulo Zanoni authored
Broadwell has different DDI buffer translations for eDP and DP, so add support for the missing eDP and keep Haswell the same. A future patch addresses the suggestion from Art to check for eDP on port D and use the eDP values there, too. v2: Make checkpatch happy. Reviewed-by:
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Art Runyan authored
Many of the DDI buffer translation values have changed for BDW. Add new translation tables and selection between HSW and BDW. v2: s/BUG/WARN/ to avoid breaking future GENs. v3: Rebase on top of the hdmi translation table changes. v4: Fix up the multiline comment while at it. Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2) Reviewed-by:
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Ben Widawsky authored
GEN8 also needs this workaround. Signed-off-by:
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Ville Syrjälä authored
Route cursor and sprite data through the pipe CSC unit on BDW. Primary plane data is already sent through the pipe CSC. Signed-off-by:
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Paulo Zanoni authored
v2: Rebased onto Paulo's MHz->kHz change. v3: Rebased on top of the Haswell pc8+ adjustements. v4: Use the exact 337.5MHz clock, should have been done as part of v2. Reviewed-by:
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Paulo Zanoni authored
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF on previous gens). v2: Rebase on to of the pipe config bpp handling rework. v3: Rebased on top of the pipe_config->dither refactoring. v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we now also build up PIPECONF completely ourselves - keeping around random stuff set by the BIOS just isn't a good idea. I've checked BDW BSpec and we already set all relevant bits. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
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Paulo Zanoni authored
So you can use the panel fitter while the power well is disabled and you also don't need to set the "pipe" bit. v2: Rebased on top of Jesse's pfit refactor, which moved pfit state into the pipe_config. v3: Rebase on top of the latest Haswell/panel fitter rework, which neatly resolves a FIXME we have in this patch here: v4: Rebase on top of the new power domain framework. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
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Paulo Zanoni authored
The platforms we currently have all have LPT LP on them. As such, we have no way to identify the new WPT PCH that will ship with Broadwell. NOTE: For all purposes relevant to the driver that this point, LPT and WPT are equivalent. Therefore there should be no need to actually change this for some time. v2: Don't assign dev_priv->num_pch_pll any more. v3: Rebase on top of the PCH detection changes for virtualized enviroments. v4: Wrote commit message Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3) Signed-off-by:
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Paulo Zanoni authored
Just like Haswell, but with the small twist that the panel fitter for pipe A is now also in the always-on power well. v2: Use the new HAS_POWER_WELL macro. v3: Rebase on top of intel_using_power_well patches. v4: This time actually update the PFIT check correctly so that the pipe A pfit is in the always-on domain. v5: Rebase on top of the VGA power domain addition. v6: Rebase on top of the new power domain infrastructure. Also pimp the commit message a bit while at it. v7: Use IS_BROADWELL instead of IS_GEN8 (Ville). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
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Paulo Zanoni authored
Just make Broadwell follow the same code paths as Haswell here, instead of running code for the even-older platforms. v2: Shuffle around Ben's vma prep work. Reviewed-by:
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