- 29 Oct, 2018 5 commits
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Ramalingam C authored
Intel HDCP2.2 registers are defined with addr offsets and bit details. v2: Replaced the arith calc with _PICK [Sean Paul] v3: No changes. v4: %s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma] v5: Added parentheses for the parameters of macro. v6: No changes v7: No changes Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/1540806351-7137-7-git-send-email-ramalingam.c@intel.com
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Ramalingam C authored
This patch adds HDCP register definitions for HDMI and DP HDCP adaptations. HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where as HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h. v2: bit_field definitions are replaced by macros. [Tomas and Jani] v3: No Changes. v4: Comments style and typos are fixed [Uma] v5: Fix for macros. v6: Adds _MS to the timeouts to represent units [Sean Paul] v7: Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma] Redundant macro is removed [Uma] Signed-off-by:
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Ramalingam C authored
This patch defines the hdcp2.2 protocol messages for authentication. v2: bit_fields are removed. Instead bitmasking used. [Tomas and Jani] prefix HDCP_2_2_ is added to the macros. [Tomas] v3: No Changes. v4: Style and spellings are fixed [Uma] v5: Fix for macros. v6: comment for Type is improved [Sean Paul] v7: %s/HDCP_2_2_LPRIME_HALF_LEN/HDCP_2_2_V_PRIME_HALF_LEN [Uma] %s/uintxx_t/uxx v8: %s/eceiver_id/receiver_id Signed-off-by:
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Ramalingam C authored
As a policy, this change considers all I915 programming failures and HW failures as ERRORS. Where as all HDCP failures due to the sink is considered as DEBUG logs. Signed-off-by:
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Ramalingam C authored
Considering significant number of HDCP specific variables, it will be clean to have separate struct for HDCP. New structure called intel_hdcp is added within intel_connector. v2: struct hdcp statically allocated. [Sean Paul] enable and disable function parameters are retained.[Sean Paul] v3: No Changes. v4: Commit msg is rephrased [Uma] v5: Comment for mutex definition. v6: hdcp_ prefix from all intel_hdcp members are removed [Sean Paul] inline function intel_hdcp_to_connector is defined [Sean Paul] v7: %s/uint64_t/u64 v8: Rebased Signed-off-by:
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- 26 Oct, 2018 6 commits
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Chris Wilson authored
A danger encountered when resetting the seqno (using debugfs/i915_next_seqno) is that as we change the breadcrumb stored in the HWSP, it may be inspected by the signaler thread leading to confusion in our sanity checks. <0> [136.331342] i915/sig-347 3..s1 136336154us : execlists_submission_tasklet: rcs0 awake?=1, active=5 <0> [136.331373] i915/sig-347 3d.s2 136336155us : process_csb: rcs0 cs-irq head=5, tail=0 <0> [136.331402] i915/sig-347 3d.s2 136336155us : process_csb: rcs0 csb[0]: status=0x00000018:0x00000002, active=0x5 <0> [136.331434] i915/sig-347 3d.s2 136336156us : process_csb: rcs0 out[0]: ctx=2.1, global=219 (fence 46:8455) (current 219), prio=0 <0> [136.331466] i915/sig-347 3d.s2 136336156us : process_csb: rcs0 completed ctx=2 <0> [136.332027] gem_exec-1049 0.... 136336246us : reset_all_global_seqno.part.5: rcs0 seqno 219 (current 219) -> -43 <0> [136.332056] gem_exec-1049 0.... 136336251us : reset_all_global_seqno.part.5: bcs0 seqno 183 (current 183) -> -43 <0> [136.332085] gem_exec-1049 0.... 136336255us : reset_all_global_seqno.part.5: vcs0 seqno 191 (current 191) -> -43 <0> [136.332114] gem_exec-1049 0.... 136336259us : reset_all_global_seqno.part.5: vcs1 seqno 180 (current 180) -> -43 <0> [136.332143] gem_exec-1049 0.... 136336262us : reset_all_global_seqno.part.5: vecs0 seqno 212 (current 212) -> -43 <0> [136.332174] i915/sig-347 3.... 136336280us : intel_breadcrumbs_signaler: intel_breadcrumbs_signaler:673 GEM_BUG_ON(!i915_request_completed(rq)) Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181024104939.2861-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Use the live_test struct to record the reset count before and compare it at the end of the test to assert that no mystery hang occurred during the test. v2: Check per-engine resets as well Signed-off-by:
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Tvrtko Ursulin authored
Upcoming GuC code will need to read the fused off engine masks as well, and will also want to have them as enabled instead of disabled masks. To consolidate the read-out place we can store them in this fashion inside INTEL_INFO so they can be easily referenced in the future. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018104106.30147-1-tvrtko.ursulin@linux.intel.com
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Chris Wilson authored
Beware mixing unsigned long constants and 64b values, as on 32b the constant will be zero extended and discard the high 32b when used as a mask! Reported-by:
Sergii Romantsov <sergii.romantsov@globallogic.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181025091823.20571-2-chris@chris-wilson.co.uk
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Chris Wilson authored
Since we use a 64b virtual GTT irrespective of the system, we want to ensure that the GTT computations remains 64b even on 32b systems, including treatment of huge virtual pages. No code generation changes on 64b: Reported-by:
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Clint Taylor authored
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value mode instead of HDMI specification values. V2: Fix 88.2 Hz N value Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1540493521-1746-2-git-send-email-clinton.a.taylor@intel.com
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- 25 Oct, 2018 1 commit
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Imre Deak authored
In order to ensure that our system suspend and resume callbacks are called in the correct order wrt. those of the HDA driver add a device link to the HDA driver during audio component binding time. With i915 as the supplier and HDA as the consumer the PM framework will guarantee the HDA->i915 suspend (and shutdown) and i915->HDA resume order. Atm, the lack of this ordering is not a problem, since all the i915 suspend/resume steps that need to be ordered wrt. the HDA driver's suspend/resume steps are separated out to the i915 suspend_late/resume_early hooks. That will change in a follow-up patchset where we'll need this ordering guarantee for steps that are in the i915 suspend/resume hooks (and which can't be moved to suspend_late/resume_early for other reasons). So this patch is a preparation for that follow-up patchset. The change also allows us to move towards removing the i915 suspend_late/resume_early hooks alltogether. Since we only need to ensure the ordering during suspend/resume and not during driver probing create the link with DL_FLAG_STATELESS. Since the probe time ordering has to be optional we use the component framework for that. Similarly for runtime PM we depend on the audio driver getting/putting an i915 runtime PM reference whenever it needs it (along with the proper i915 display power domain) via the audio component ops get_power / put_power hooks. So we create the device link without DL_FLAG_PM_RUNTIME. v2: (Ville) - Add a note to the commit message about not using the device link runtime PM ordering. - Handle the error return from device_link_add(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181023144310.8272-1-imre.deak@intel.com
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- 24 Oct, 2018 15 commits
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Chris Wilson authored
make W=1 caught the implicit prototypes (as would sparse): drivers/gpu/drm/i915/intel_sprite.c:462:1: error: no previous prototype for ‘skl_update_plane’ [-Werror=missing-prototypes] skl_update_plane(struct intel_plane *plane, ^~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/intel_sprite.c:487:1: error: no previous prototype for ‘skl_disable_plane’ [-Werror=missing-prototypes] skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) ^~~~~~~~~~~~~~~~~ Fixes: 1e364f90 ("drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.") Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181024105402.18915-1-chris@chris-wilson.co.uk
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Lionel Landwerlin authored
Forgot to add the description of this option in a previous commit. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: cd956bfc ("drm/i915/perf: add a parameter to control the size of OA buffer") Reviewed-by:
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Ville Syrjälä authored
The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to the appropriate platforms. This was especially harsh on GLK since we don't even try to read the DIMM information on that platforms, hence valid_dimm was always false and thus we always tried to apply the w/a. Furthermore the w/a pushed the level 0 latency above the level 1 latency, which doesn't really make sense. v2: Do the check when populating is_16gb_dimm (Mahesh) Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 86b59287 ("drm/i915: Implement 16GB dimm wa for latency level-0") Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by:
Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
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Maarten Lankhorst authored
Now that we implemented support for planar formats on gen11, we can finally advertise it. Changes since v1: - Re-add change to skl_plane_has_planar(), was lost in rebase noise. Signed-off-by:
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Maarten Lankhorst authored
The UV plane is the master plane that does all color correction etc. It needs to be programmed with the dimensions for color plane 1 (UV). The Y plane just feeds the Y pixels to it. Program the scaler from the master only, and set PLANE_CTL_YUV420_Y_PLANE on the slave plane. Changes since v1: - Make a common skl_program_plane, and use it for both plane updates. Changes since v2: - Make color_plane explicit, to clarify skl_update_plane(). (Ville) Signed-off-by:
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Maarten Lankhorst authored
We configure the chroma upsampler with the same chroma siting as used by the scaler for consistency, the chroma upsampler is used instead of the scaler for YUV 4:2:0 on ICL's HDR planes. Signed-off-by:
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Maarten Lankhorst authored
The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma upsampler to upscale YUV420 to YUV444 and the scaler should only be used for upscaling. Because of this we shouldn't program the scalers in planar mode if NV12 and the chroma upsampler are used. Instead program the scalers like on normal planes. Sprite 2 and 3 have no dedicated scaler, and need to program the selected Y plane in the scaler mode. Changes since v1: - Make the comment less confusing. Changes since v2: - Fix checkpatch warning (Matt) - gen10- -> Pre-gen11 (Ville) - PS_SCALER_MODE_PACKED -> PS_SCALER_MODE_NORMAL. (Matt) - Add comment about scaler mode in intel_atomic_setup_scaler(). (Matt) - Rename need_scaling to need_scaler. (Matt) - Move the crtc need_scaling check to skl_update_scaler_crtc(). Signed-off-by:
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Maarten Lankhorst authored
Skylake style watermarks program the UV parameters into wm->uv_wm, and have a separate DDB allocation for UV blocks into the same plane. Gen11 watermarks have a separate plane for Y and UV, with separate mechanisms. The simplest way to make it work is to keep the current way of programming watermarks and calculate the Y and UV plane watermarks from the master plane. Changes since v1: - Constify crtc_state where possible. - Make separate paths for planar formats in skl_build_pipe_wm() (Matt) - Make separate paths for calculating total data rate. (Matt) - Make sure UV watermarks are unused on gen11+ by adding a WARN. (Matt) Signed-off-by:
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Maarten Lankhorst authored
To make NV12 working on icl, we need to update 2 planes simultaneously. I've chosen to do this in the CRTC step after plane validation is done, so we know what planes are (in)visible. The linked Y plane will get updated in intel_plane_update_planes_on_crtc(), by the call to update_slave, which gets the master's plane_state as argument. The link requires both planes for atomic_update to work, so make sure skl_ddb_add_affected_planes() adds both states. Changes since v1: - Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers. - Put all the state updating login in intel_plane_atomic_check_with_state(). - Clean up changes in intel_plane_atomic_check(). Changes since v2: - Fix intel_atomic_get_old_plane_state() to actually return old state. - Move visibility changes to preparation patch. - Only try to find a Y plane on gen11, earlier platforms only require a single plane. Changes since v3: - Fix checkpatch warning about to_intel_crtc() usage. - Add affected planes from icl_add_linked_planes() before check_planes(), it's a cleaner way to do this. (Ville) Changes since v4: - Clear plane links in icl_check_nv12_planes() for clarity. - Only pass crtc_state to icl_check_nv12_planes(). - Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes. - Rename aux to linked. (Ville) Signed-off-by:
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Maarten Lankhorst authored
Gen11 supports 7 planes + 1 cursor on each pipe. Bump I915_MAX_PLANES to 8, and set num_sprites correctly. Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018115134.9061-3-maarten.lankhorst@linux.intel.com
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Maarten Lankhorst authored
On gen11, we can definitely smash the 32-bits barrier with just a when we enable all planes in the next patch. Changes since v1: - Use div64_u64 (ickle). Signed-off-by:
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Ramalingam C authored
When a HDCP authentication is in progress, if the display sink is hot unplugged, all DDC/AUX transaction related to the HDCP authentication will fail. This patch moves those kind of HDCP DDC/AUX failures into the debug logs instead of errors. v2: Bksv invalid state is provided as debug msg Signed-off-by:
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Ramalingam C authored
Add a debugfs entry for providing the hdcp capabilities of the sink connected to the HDCP capable connectors. v2: Squashed the sink's hdcp capability into this patch. [Daniel] Signed-off-by:
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Ramalingam C authored
HDCP check link is invoked only on CP_IRQ detection, instead of all short pulses. v3: No Changes. v4: Added sean in cc and collected the reviewed-by received. v5: No Change. v6: No Change. v7: No Change. v8: Rebased. Signed-off-by:
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Ramalingam C authored
For reusability purpose, this patch implements the hdcp1.4 bksv's read and validation as a functions. For detecting the HDMI panel's HDCP capability this fucntions will be used. v2: Rebased. v3: No Changes. v4: inline tag is removed with modified error msg. v5: No Changes. v6: No Changes. v7: Realigned the code. Signed-off-by:
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- 23 Oct, 2018 13 commits
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Chris Wilson authored
Propagate the timeout on transferring the fw back to the caller where it may act upon it, usually by restarting the xfer before failing. v2: Simplify the wait to only wait upon the guc signaling completion, with an assertion that the fw xfer must have completed for it to be ready! Testcase: igt/drv_selftest/live_hangcheck Signed-off-by:
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Ville Syrjälä authored
Remove the local lvds fixed mode pointer from the sdvo encoder structure and instead utilize intel_panel like everyone else. v2: intel_sdvo_destroy() is gone Signed-off-by:
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Ville Syrjälä authored
Let's run through the entire plane check even when the plane is invisible due to zero constant alpha. This makes for more consistent behaviour since we check the src/dst coordinates, stride etc. against the hardware limits. Signed-off-by:
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Ville Syrjälä authored
The SKL+ NV12 src width alignment w/a is still living in an odd place. Everything else was already relocated closer to the main plane check function. Move this workaround as well. As a bonus we avoid the funky rotated vs. not mess with the src coordinates as this now gets checked before we rotate the coordinates. Signed-off-by:
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Lionel Landwerlin authored
The way our hardware is designed doesn't seem to let us use the MI_RECORD_PERF_COUNT command without setting up a circular buffer. In the case where the user didn't request OA reports to be available through the i915 perf stream, we can set the OA buffer to the minimum size to avoid consuming memory which won't be used by the driver. v2: Simplify oa buffer size exponent selection (Chris) Reuse vma size field (Lionel) v3: Restrict size opening parameter to values supported by HW (Chris) v4: Drop out of date comment (Matt) Add debug message when buffer size is rejected (Matt) Signed-off-by: -
Lionel Landwerlin authored
We want to use some of the properties of the perf stream to program the hardware in a later commit. v2: Pass only perf stream as argument (Matthew) Signed-off-by:
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Lionel Landwerlin authored
We initialize the OA buffer everytime we enable the OA unit (first call in gen[78]_oa_enable), so we don't need to initialize when preparing the metric set. Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181023100707.31738-3-lionel.g.landwerlin@intel.com
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Lionel Landwerlin authored
Lucas submitted a patch to generator script, so just reflecting the change here. Signed-off-by:
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Daniele Ceraolo Spurio authored
commit e346a991 ("drm/i915/guc: drop negative doorbell alloc selftest") removed the negative case from the selftest and left no code between the goto from the positive case of the test and the label itself, so we can get rid of it. Reported-by:
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Daniele Ceraolo Spurio authored
We stopped supporting fallback to execlists in commit 121981fa (drm/i915/guc: Combine enable_guc_loading|submission modparams). We do instead reset and retry in some cases, depending on the workarounds required by the platform. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by:
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Daniele Ceraolo Spurio authored
A collection of very small cleanups/improvements around doorbell checking that do not deserve their own patch: - Move doorbell-related HW defs to intel_guc_reg.h - use GUC_NUM_DOORBELLS instead of GUC_DOORBELL_INVALID where appropriate - do not stop on error in guc_verify_doorbells - do not print drbreg on error: the only content of the register apart from the valid bit is the lower part of the physical memory address, which we can't use even if valid because we don't know which descriptor it came from (since the doorbell is in an unexpected state) - Move the checking of doorbell valid bit to a common helper. v2: add more cleanups (move defs, use GUC_NUM_DOORBELLS, don't stop in guc_verify_doorbells) (Michal) v3: move more things to intel_guc_reg, redefine GUC_DOORBELL_INVALID (Michal), drop guc_doorbell_qw since it just duplicates guc_doorbell_info Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: -
Daniele Ceraolo Spurio authored
Cacheline selection is only needed if we actually manage to reserve a doorbell. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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Daniele Ceraolo Spurio authored
The 2 functions don't create or destroy anything, they just update the doorbell state in memory. Use init and fini instead for clarity. Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by:
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