1. 29 Mar, 2022 1 commit
    • Mario Limonciello's avatar
      rtc: mc146818-lib: Fix the AltCentury for AMD platforms · 3ae8fd41
      Mario Limonciello authored
      Setting the century forward has been failing on AMD platforms.
      There was a previous attempt at fixing this for family 0x17 as part of
      commit 7ad295d5 ("rtc: Fix the AltCentury value on AMD/Hygon
      platform") but this was later reverted due to some problems reported
      that appeared to stem from an FW bug on a family 0x17 desktop system.
      
      The same comments mentioned in the previous commit continue to apply
      to the newer platforms as well.
      
      ```
      MC146818 driver use function mc146818_set_time() to set register
      RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
      reset value on Intel platform to 0x7.
      
      While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
      DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
      as reserved.
      
      DV0 is set to 1, it will select Bank 1, which will disable AltCentury
      register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
      (AltCentury), the CMOS write will be failed on code:
      CMOS_WRITE(century, acpi_gbl_FADT.century).
      
      Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
      enable AltCentury(0x32) register writing and finally setup century as
      expected.
      ```
      
      However in closer examination the change previously submitted was also
      modifying bits 5 & 6 which are declared reserved in the AMD documentation.
      So instead modify just the DV0 bank selection bit.
      
      Being cognizant that there was a failure reported before, split the code
      change out to a static function that can also be used for exclusions if
      any regressions such as Mikhail's pop up again.
      
      Cc: Jinke Fan <fanjinke@hygon.cn>
      Cc: Mikhail Gavrilov <mikhail.v.gavrilov@gmail.com>
      Link: https://lore.kernel.org/all/CABXGCsMLob0DC25JS8wwAYydnDoHBSoMh2_YLPfqm3TTvDE-Zw@mail.gmail.com/
      Link: https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdfSigned-off-by: default avatarRaul E Rangel <rrangel@chromium.org>
      Signed-off-by: default avatarMario Limonciello <mario.limonciello@amd.com>
      Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
      Link: https://lore.kernel.org/r/20220111225750.1699-1-mario.limonciello@amd.com
      3ae8fd41
  2. 25 Mar, 2022 4 commits
  3. 23 Mar, 2022 35 commits