- 28 Nov, 2011 4 commits
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Anton Blanchard authored
On a 64bit book3s machine I have an oops from a system reset that claims the book3e CE bit was set: MSR: 8000000000021032 <ME,CE,IR,DR> CR: 24004082 XER: 00000010 On a book3s machine system reset sets IBM bit 46 and 47 depending on the power saving mode. Separate the definitions by type and for completeness add the rest of the bits in. Signed-off-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Matthew McClintock authored
In lieu of having multiple similiar lines, we can just have one generic cpu-as line for CONFIG_ALTIVEC Signed-off-by: -
Dmitry Eremin-Solenikov authored
CPC925/CPC945 use special window to access host bridge functionality of u3-ht. Provide a way to access this device. Signed-off-by:
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by:
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sukadev@linux.vnet.ibm.com authored
As described in the help text in the patch, this token restricts general access to /dev/mem as a way of increasing the security. Specifically, access to exclusive IOMEM and kernel RAM is denied unless CONFIG_STRICT_DEVMEM is set to 'n'. Implement the 'devmem_is_allowed()' interface for Powerpc. It will be called from range_is_allowed() when userpsace attempts to access /dev/mem. This patch is based on an earlier patch from Steve Best and with input from Paul Mackerras and Scott Wood. [BenH] Fixed a typo or two and removed the generic change which should be submitted as a separate patch Signed-off-by:Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by:
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- 25 Nov, 2011 30 commits
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Benjamin Herrenschmidt authored
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Justin P. Mattock authored
The patch below removes an extra semicolon. Signed-off-by:
Justin P. Mattock <justinmattock@gmail.com> CC: linuxppc-dev@lists.ozlabs.org CC: Paul Mackerras <paulus@samba.org> Signed-off-by:
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Ananth N Mavinakayanahalli authored
On Fri, Nov 11, 2011 at 10:17:55AM +0530, Ananth N Mavinakayanahalli wrote: > > > > At this rate we're going to end up with no bits left for CPU features > > way too quickly... Especially for something we only care about once at > > boot time. > > > > Wouldn't CPU_FTR_PPCAS_ARCH_V2 be a good enough test ? > > /me checks Cell manuals... yes, that test would be good enough. I will > cook up a patch to use this. Here it is... Signed-off-by: -
Benjamin Herrenschmidt authored
This adds support for p7IOC (and possibly other IODA v1 IO Hubs) using OPAL v2 interfaces. We completely take over resource assignment and assign them using an algorithm that hands out device BARs in a way that makes them fit in individual segments of the M32 window of the bridge, which enables us to assign individual PEs to devices and functions. The current implementation gives out a PE per functions on PCIe, and a PE for the entire bridge for PCIe to PCI-X bridges. This can be adjusted / fine tuned later. We also setup DMA resources (32-bit only for now) and MSIs (both 32-bit and 64-bit MSI are supported). The DMA allocation tries to divide the available 256M segments of the 32-bit DMA address space "fairly" among PEs. This is done using a "weight" heuristic which assigns less value to things like OHCI USB controllers than, for example SCSI RAID controllers. This algorithm will probably want some fine tuning for specific devices or device types. Signed-off-by: -
Benjamin Herrenschmidt authored
It advertises "host bridge" instead of "PCI to PCI bridge" which confuses the Linux probe code. Signed-off-by: -
Benjamin Herrenschmidt authored
This is used for newer IO Hubs such as p7IOC. Signed-off-by: -
Benjamin Herrenschmidt authored
When PCI_REASSIGN_ALL_RSRC is set, we used to clear all bus resources at the beginning of survey and re-allocate them later. This changes it so instead, during early fixup, we mark all resources as IORESOURCE_UNSET and move them down to be 0-based. Later, if bus resources are still unset at the beginning of the survey, then we clear them. This shouldn't impact the re-assignment case on 4xx, but will enable us to have the platform do some custom resource assignment before the survey, by clearing individual resources IORESOURCE_UNSET bit. Also limits the clutter in the kernel log from fixup when re-assigning since we don't care about the offset applied to the BAR values in this case. Signed-off-by: -
Benjamin Herrenschmidt authored
Some platforms need to perform resource allocation using a custom algorithm due to HW constraints, or may want to tweak things globally below a host bridge. For example OPAL support for IODA will need to perform a resource allocation pass that applies IODA specific segmentation constraints to MMIO which cannot be done simply using the kernel generic resource management code. Signed-off-by: -
Geoff Thorpe authored
This adds a pgprot combination required by some cache-enabled IO device mappings, such as Freescale datapath (QMan and BMan) portals. Signed-off-by:
Geoff Thorpe <geoff@geoffthorpe.net> Signed-off-by:
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Thomas Gleixner authored
All interrupts which must be non threaded are marked IRQF_NO_THREAD. So it's safe to allow force threaded handlers. Signed-off-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
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Thomas Gleixner authored
IPI handlers cannot be threaded. Remove the obsolete IRQF_DISABLED flag (see commit e58aa3d2) while at it. Signed-off-by:
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Thomas Gleixner authored
Cascade handlers must run in hard interrupt context. Signed-off-by:
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Thomas Gleixner authored
Cascade interrupt must run in hard interrupt context. Signed-off-by:
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Ravi K. Nittala authored
The RTAS firmware flash update is conducted using an RTAS call that is serialized by lock_rtas() which uses spin_lock. While the flash is in progress, rtasd performs scan for any RTAS events that are generated by the system. rtasd keeps scanning for the RTAS events generated on the machine. This is performed via workqueue mechanism. The rtas_event_scan() also uses an RTAS call to scan the events, eventually trying to acquire the spin_lock before issuing the request. The flash update takes a while to complete and during this time, any other RTAS call has to wait. In this case, rtas_event_scan() waits for a long time on the spin_lock resulting in a soft lockup. Fix: Just before the flash update is performed, the queued rtas_event_scan() work item is cancelled from the work queue so that there is no other RTAS call issued while the flash is in progress. After the flash completes, the system reboots and the rtas_event_scan() is rescheduled. Signed-off-by:
Suzuki Poulose <suzuki@in.ibm.com> Signed-off-by:
Ravi Nittala <ravi.nittala@in.ibm.com> Reported-by:
Divya Vikas <divya.vikas@in.ibm.com> Signed-off-by:
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Jimi Xenidis authored
This patch add the Chroma platform to WSP/PowerEN, which is a PCIe card (a defconfig is included). The card includes an H8 service processor that is used to manage the card. The H8 is connected over the second serial UART on the PowerEN chip so this patch includes a simple 16550 driver to enable communication, mostly for "power off" and "rebooting". This patch also includes a, WSP specific, "halt" method that will shut of all A2 cores but still leave power on at the chip level. This is desirable, especially if you wish to interrogate the chip with a hardware probe after the halt. Signed-off-by:
Jimi Xenidis <jimix@pobox.com> Signed-off-by:
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Jimi Xenidis authored
Sorry, there was a typo in the #if signed-off-by:
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Jimi Xenidis authored
The 'u' command will print the TLB on book3e parts and the SLB on Book3s parts, but the help system doesn't say that correctly. Signed-off-by:
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Jimi Xenidis authored
This patch adds a fault handler that responds to illegal Coprocessor types. Currently all CTs are treated and illegal. There are two ways to report the fault back to the application. If the application used the record form ("icswx.") then the architected "reject" is emulated. If the application did not used the record form ("icswx") then it is selectable by config whether the failure is silent (as architected) or a SIGILL is generated. In all cases pr_warn() is used to log the bad CT. Signed-off-by: -
Jimi Xenidis authored
ICSWX is also used by the A2 processor to access coprocessors, although not all "chips" that contain A2s have coprocessors. Signed-off-by:
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Jimi Xenidis authored
Some processors, like embedded, that already have a PID register that is managed by the system. This patch separates the ACOP and PID processing into separate files so that the ACOP code can be shared. Signed-off-by:
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Florian Fainelli authored
libio.h is not provided by uClibc, in order to be able to test the definition of __UCLIBC__ we need to include stdlib.h, which also includes stddef.h, providing the definition of 'NULL'. Signed-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
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Julia Lawall authored
np is initialized to the result of calling a function that calls of_node_get, so of_node_put should be called before the pointer is dropped. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e,e1,e2; @@ * e = \(of_find_node_by_type\|of_find_node_by_name\)(...) ... when != of_node_put(e) when != true e == NULL when != e2 = e e = e1 // </smpl> Signed-off-by:
Julia Lawall <julia@diku.dk> Signed-off-by:
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Julia Lawall authored
np is initialized to the result of calling a function that calls of_node_get, so of_node_put should be called before the pointer is dropped. The semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression e,e1,e2; @@ * e = \(of_find_node_by_type\|of_find_node_by_name\)(...) ... when != of_node_put(e) when != true e == NULL when != e2 = e e = e1 // </smpl> Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Milton Miller authored
Some pseries IOMMUs cache TCEs but don't snoop when the TCEs are changed in memory, hence we need manually invalidate in software. This adds code to do the invalidate. It keys off a device tree property to say where the to do the MMIO for the invalidate and some information on what the format of the invalidate including some magic routing info. it_busno get overloaded with this magic routing info and it_index with the MMIO address for the invalidate command. This then gets hooked into the building and freeing of TCEs. This is only useful on bare metal pseries. pHyp takes care of this when virtualised. Based on patch from Milton with cleanups from Mikey. Signed-off-by:
Milton Miller <miltonm@bga.com> Signed-off-by:
Michael Neuling <mikey@neuling.org> Signed-off-by:
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Anton Blanchard authored
decrementer_check_overflow is called from arch_local_irq_restore so we want to make it as light weight as possible. As such, turn decrementer_check_overflow into an inline function. To avoid a circular mess of includes, separate out the two components of struct decrementer_clock and keep the struct clock_event_device part local to time.c. The fast path improves from: arch_local_irq_restore 0: mflr r0 4: std r0,16(r1) 8: stdu r1,-112(r1) c: stb r3,578(r13) 10: cmpdi cr7,r3,0 14: beq- cr7,24 <.arch_local_irq_restore+0x24> ... 24: addi r1,r1,112 28: ld r0,16(r1) 2c: mtlr r0 30: blr to: arch_local_irq_restore 0: std r30,-16(r1) 4: ld r30,0(r2) 8: stb r3,578(r13) c: cmpdi cr7,r3,0 10: beq- cr7,6c <.arch_local_irq_restore+0x6c> ... 6c: ld r30,-16(r1) 70: blr Unfortunately we still setup a local TOC (due to -mminimal-toc). Yet another sign we should be moving to -mcmodel=medium. Signed-off-by: -
Anton Blanchard authored
Fix some formatting issues and use the DECREMENTER_MAX define instead of 0x7fffffff. Signed-off-by:
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Anton Blanchard authored
The clockevents code uses max_delta_ns to avoid calling a clockevent with too large a value. Remove the redundant version of this in the timer_interrupt code. Signed-off-by:
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Anton Blanchard authored
Use clocksource_register_hz which calculates the shift/mult factors for us. Also remove the shift = 22 assumption in vsyscall_update - thanks to Paul Mackerras and John Stultz for catching that. Signed-off-by:
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Anton Blanchard authored
We can use clockevents_calc_mult_shift instead of doing all the work ourselves. Signed-off-by:
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Anton Blanchard authored
When re-enabling interrupts we have code to handle edge sensitive decrementers by resetting the decrementer to 1 whenever it is negative. If interrupts were disabled long enough that the decrementer wrapped to positive we do nothing. This means interrupts can be delayed for a long time until it finally goes negative again. While we hope interrupts are never be disabled long enough for the decrementer to go positive, we have a very good test team that can drive any kernel into the ground. The softlockup data we get back from these fails could be seconds in the future, completely missing the cause of the lockup. We already keep track of the timebase of the next event so use that to work out if we should trigger a decrementer exception. Signed-off-by:
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- 24 Nov, 2011 6 commits
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Chuck Meade authored
The UCC UART driver is missing a call to uart_update_timeout(). Without this call, attempting to close the port after outputting large amounts of data (i.e. using tty and uart buffering) results in long timeouts before the port will actually be shut down. For example, cat a large file to a UCC UART port. With the current driver, the port will stay open for 30 seconds after the last byte of data is output. But with this patch, the port is closed as expected, just after the data has been output (tx fifos empty). Signed-off-by:
Chuck Meade <chuck@ThePTRGroup.com> Acked-by:
Timur Tabi <timur@freescale.com> Signed-off-by:
Kumar Gala <galak@kernel.crashing.org>
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Timur Tabi authored
On Freescale parts with multiple MSI controllers, the controllers are combined into one "pool" of interrupts. Whenever a device requests an MSI interrupt, the next available interrupt from the pool is selected, regardless of which MSI controller the interrupt is from. This works because each PCI bus has an ATMU to all of CCSR, so any PCI device can access any MSI interrupt register. The fsl,msi property is used to specify that a given PCI bus should only use a specific MSI device. This is necessary, for example, with the Freescale hypervisor, because the MSI devices are assigned to specific partitions. Ideally, we'd like to be able to assign MSI devices to PCI busses within the MSI or PCI layers. However, there does not appear to be a mechanism to do that. Whenever the MSI layer wants to allocate an MSI interrupt to a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we could register an MSI device with a specific PCI bus. So instead we remember the phandles of each MSI device, and we use that to limit our search for an available interrupt. Whenever we are asked to allocate a new interrupt for a PCI device, we check the fsl,msi property of the PCI bus for that device. If it exists, then as we are looping over all MSI devices, we skip the ones that don't have a matching phandle. Signed-off-by:
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Kumar Gala authored
The file name is already scoped by the directory its in. Signed-off-by: -
Kumar Gala authored
P1010RDB & P1023RDS can use the new mpc85xx_common_publish_devices(). Also move 'fsl,srio' into the list of standard buses. Signed-off-by: -
Dmitry Eremin-Solenikov authored
85xx board files have a lot of duplication in *_publish_devices()/ *_declare_of_platform_devices() functions. Merge that into a single function common to most of the boards. Signed-off-by:
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Dmitry Eremin-Solenikov authored
Separate handling of CPM2 PIC initialization to mpc85xx_cpm2_pic_init() function. Signed-off-by:
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