- 15 Aug, 2019 6 commits
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Chengming Gui authored
add arcturus_is_dpm_running function Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Kevin Wang <kevin1.wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Chengming Gui authored
remove redundancy debug log about smu unsupported features Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Christoph Hellwig <hch@lst.de> Signed-off-by:
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Christoph Hellwig authored
Use dma_set_mask_and_coherent to set both masks in one go, and remove the no longer required fallback, as the kernel now always accepts larger than required DMA masks. Fail the driver probe if we can't set the DMA mask, as that means the system can only support a larger mask. Reviewed-by:
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Christoph Hellwig authored
amdgpu uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
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Christoph Hellwig authored
radeon uses a need_dma32 flag to indicate to the drm core that some allocations need to be done using GFP_DMA32, but it only checks the device addressing capabilities to make that decision. Unfortunately PCIe root ports that have limited addressing exist as well. Use the dma_addressing_limited instead to also take those into account. Reviewed-by:
Atish Patra <Atish.Patra@wdc.com> Signed-off-by:
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- 12 Aug, 2019 34 commits
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Alex Deucher authored
The current code won't likely work on production hw when it ships so leave it as experimental until it's ready. Acked-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
Renoir need not load mec2 jump table with psp. Acked-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
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Huang Rui authored
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use direct loading for the moment till the issue is addressed. Acked-by:
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Aaron Liu authored
By default, set amdgpu ucode type to AMDGPU_FW_LOAD_PSP. Acked-by:
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Aaron Liu authored
enable gfx_v9_0_init_lbpw for renoir Acked-by:
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Aaron Liu authored
enable gfx power gating for renoir Acked-by:
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Aaron Liu authored
enable gfx&common clock gating for renoir Acked-by:
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Leo Liu authored
Thus enable VCN2.0 for Renoir Acked-by:
Leo Liu <leo.liu@amd.com> Reviewed-by:
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Leo Liu authored
Add VCN range aperture to NBIO 7.0 v2: rebase (Alex) Acked-by:
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Leo Liu authored
By adding new Renoir VCN firmware Acked-by:
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Huang Rui authored
This patch adds sdma golden settings for renoir asic. Acked-by:
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Huang Rui authored
This patch adds gfx golden settings for renoir real asic. v2: update settings (Alex) Acked-by:
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Aaron Liu authored
1. Add psp ip block 2. Use direct loading type by default and it can also config psp loading type. 3. Bypass sos fw loading and xgmi&ras interface v2: drop TA loading Acked-by:
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Aaron Liu authored
add gfx_v9_0_rlc_funcs for renoir Acked-by:
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Aaron Liu authored
add asic funcs for renoir, init soc15_asic_funcs Acked-by:
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Aaron Liu authored
Acked-by:
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Aaron Liu authored
In renoir's ih model, there's a change in mmIH_CHICKEN register, that limits IH to use physical address directly. Those chicken bits need to be programmed first. Acked-by:
Hawking Zhang <Hawking.Zhang@amd.com> Acked-by:
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Huang Rui authored
Add Renoir PCI id support. Acked-by:
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Huang Rui authored
Enable ip blocks for renoir. Acked-by:
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Huang Rui authored
Add renoir checks to appropriate places. Acked-by:
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Huang Rui authored
Add Renoir checks to gfx9 code. Acked-by:
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Huang Rui authored
This patch sets fw load type as direct for renoir for the moment. Will switch to psp when psp is ready. Acked-by:
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Huang Rui authored
Add gfx memory controller support for renoir. Acked-by:
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Huang Rui authored
This patch adds common ip support for renoir. Acked-by:
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Huang Rui authored
This patch adds renoir support for gpu_info firmware and ip block setting. Acked-by:
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Huang Rui authored
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[]. Acked-by:
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Huang Rui authored
This patch add all renoir header files. v2: clean up headers (Alex) Acked-by:
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Colin Ian King authored
The check on ret is duplicated in two places, it is redundant code. Remove it. Addresses-Coverity: ("Logically dead code") Fixes: b94afb61 ("drm/amd/powerplay: honor hw limit on fetching metrics data for navi10") Reviewed-by:Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Christophe JAILLET authored
This should be 'dce_audio_mask', not 'dce_aduio_mask'. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by:
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Alex Deucher authored
It's large and doesn't need contiguous memory. Fixes allocation failures in some cases. v2: kvfree the memory. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Pierre-Eric Pelloux-Prayer authored
The SOC15_REG_OFFSET() macro wasn't used, making the soft recovery fail. v2: use WREG32_SOC15 instead of WREG32 + SOC15_REG_OFFSET Signed-off-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by:
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Le Ma authored
Follow patch below: drm/amd/powerplay: re-define smu interface version for smu v11 Signed-off-by:Le Ma <le.ma@amd.com> Reviewed-by:
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Le Ma authored
Init MC_MGCG/LS flag. Also apply to athub CG. Signed-off-by:
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Le Ma authored
Add 2 mmhub instances CG Signed-off-by:
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