- 05 Apr, 2022 9 commits
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Angus Wang authored
[WHY] Some games experience low FPS issues when FreeSync is on and VSync is toggled to half refresh rate. [HOW] First create a function to determine workaround conditions, which is when we detect 2 or more VSync interrupts between flips and a very short VSync to flip interval. We do the workaround during VSync interrupts and set the v_total_max and min to nominal. We also cleanup after we exit the game. Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Angus Wang <Angus.Wang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Eric Bernstein authored
Remove assert that will hit during odm transition case, since this is a valid case. Tested-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
Eric Bernstein <eric.bernstein@amd.com> Signed-off-by:
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Philip Yang authored
For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have stall invalid PTEs in TC because one cache line has 8 pages. Need always flush_tlb after updating mapping. Signed-off-by:
Philip Yang <Philip.Yang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
Seems to cause a reboots or hangs on some systems. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1924 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1953 Fixes: daf8de08 ("drm/amdgpu: always reset the asic in suspend (v2)") Reviewed-by:
Lijo Lazar <lijo.lazar@amd.com> Signed-off-by:
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Haowen Bai authored
report by coccicheck: drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c:1951:2-3: Unneeded semicolon Fixes: c543dcbe ("drm/amdgpu/vcn: Add VCN ras error query support") Signed-off-by:
Haowen Bai <baihaowen@meizu.com> Signed-off-by:
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Aashish Sharma authored
Fix the kernel test robot warning below: drivers/gpu/drm/amd/amdgpu/../display/dmub/inc/dmub_cmd.h:2893:12: warning: variable 'temp' set but not used [-Wunused-but-set-variable] Replaced the assignment to the unused temp variable with READ_ONCE() macro to flush the writes. READ_ONCE() helps avoid the use of volatile and makes it obvious from the code that the read here is intentional. Also verified on x86 that the generated code is exactly the same as before. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
Aashish Sharma <shraash@google.com> Signed-off-by:
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Marko Zekovic authored
SMI clock measure API is failing on NAVI12, because sysfs node for pp_dpm_vclk is not existing. Enable sysfs node for pp_dpm_vclk for NAVI12. v2: Also enable sysfs node for pp_dpm_dclk. Reviewed-by:
Marko Zekovic <Marko.Zekovic@amd.com> Signed-off-by:
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Christian König authored
Testing the valid bit is not enough to figure out if we need to invalidate the TLB or not. During eviction it is quite likely that we move a BO from VRAM to GTT and update the page tables immediately to the new GTT address. Rework the whole function to get all the necessary parameters directly as value. Signed-off-by:
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CHANDAN VURDIGERE NATARAJ authored
[Why] Below general protection fault observed when WebGL Aquarium is run for longer duration. If drm debug logs are enabled and set to 0x1f then the issue is observed within 10 minutes of run. [ 100.717056] general protection fault, probably for non-canonical address 0x2d33302d32323032: 0000 [#1] PREEMPT SMP NOPTI [ 100.727921] CPU: 3 PID: 1906 Comm: DrmThread Tainted: G W 5.15.30 #12 d726c6a2d6ebe5cf9223931cbca6892f916fe18b [ 100.754419] RIP: 0010:CalculateSwathWidth+0x1f7/0x44f [ 100.767109] Code: 00 00 00 f2 42 0f 11 04 f0 48 8b 85 88 00 00 00 f2 42 0f 10 04 f0 48 8b 85 98 00 00 00 f2 42 0f 11 04 f0 48 8b 45 10 0f 57 c0 <f3> 42 0f 2a 04 b0 0f 57 c9 f3 43 0f 2a 0c b4 e8 8c e2 f3 ff 48 8b [ 100.781269] RSP: 0018:ffffa9230079eeb0 EFLAGS: 00010246 [ 100.812528] RAX: 2d33302d32323032 RBX: 0000000000000500 RCX: 0000000000000000 [ 100.819656] RDX: 0000000000000001 RSI: ffff99deb712c49c RDI: 0000000000000000 [ 100.826781] RBP: ffffa9230079ef50 R08: ffff99deb712460c R09: ffff99deb712462c [ 100.833907] R10: ffff99deb7124940 R11: ffff99deb7124d70 R12: ffff99deb712ae44 [ 100.841033] R13: 0000000000000001 R14: 0000000000000000 R15: ffffa9230079f0a0 [ 100.848159] FS: 00007af121212640(0000) GS:ffff99deba780000(0000) knlGS:0000000000000000 [ 100.856240] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 100.861980] CR2: 0000209000fe1000 CR3: 000000011b18c000 CR4: 0000000000350ee0 [ 100.869106] Call Trace: [ 100.871555] <TASK> [ 100.873655] ? asm_sysvec_reschedule_ipi+0x12/0x20 [ 100.878449] CalculateSwathAndDETConfiguration+0x1a3/0x6dd [ 100.883937] dml31_ModeSupportAndSystemConfigurationFull+0x2ce4/0x76da [ 100.890467] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.895173] ? kallsyms_lookup_buildid+0xc8/0x163 [ 100.899874] ? __sprint_symbol+0x80/0x135 [ 100.903883] ? dm_update_plane_state+0x3f9/0x4d2 [ 100.908500] ? symbol_string+0xb7/0xde [ 100.912250] ? number+0x145/0x29b [ 100.915566] ? vsnprintf+0x341/0x5ff [ 100.919141] ? desc_read_finalized_seq+0x39/0x87 [ 100.923755] ? update_load_avg+0x1b9/0x607 [ 100.927849] ? compute_mst_dsc_configs_for_state+0x7d/0xd5b [ 100.933416] ? fetch_pipe_params+0xa4d/0xd0c [ 100.937686] ? dc_fpu_end+0x3d/0xa8 [ 100.941175] dml_get_voltage_level+0x16b/0x180 [ 100.945619] dcn30_internal_validate_bw+0x10e/0x89b [ 100.950495] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.955285] ? resource_build_scaling_params+0x98b/0xb8c [ 100.960595] ? dcn31_validate_bandwidth+0x68/0x1fc [ 100.965384] dcn31_validate_bandwidth+0x9a/0x1fc [ 100.970001] dc_validate_global_state+0x238/0x295 [ 100.974703] amdgpu_dm_atomic_check+0x9c1/0xbce [ 100.979235] ? _printk+0x59/0x73 [ 100.982467] drm_atomic_check_only+0x403/0x78b [ 100.986912] drm_mode_atomic_ioctl+0x49b/0x546 [ 100.991358] ? drm_ioctl+0x1c1/0x3b3 [ 100.994936] ? drm_atomic_set_property+0x92a/0x92a [ 100.999725] drm_ioctl_kernel+0xdc/0x149 [ 101.003648] drm_ioctl+0x27f/0x3b3 [ 101.007051] ? drm_atomic_set_property+0x92a/0x92a [ 101.011842] amdgpu_drm_ioctl+0x49/0x7d [ 101.015679] __se_sys_ioctl+0x7c/0xb8 [ 101.015685] do_syscall_64+0x5f/0xb8 [ 101.015690] ? __irq_exit_rcu+0x34/0x96 [How] It calles populate_dml_pipes which uses doubles to initialize. Adding FPU protection avoids context switch and probable loss of vba context as there is potential contention while drm debug logs are enabled. Signed-off-by:
CHANDAN VURDIGERE NATARAJ <chandan.vurdigerenataraj@amd.com> Reviewed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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- 01 Apr, 2022 31 commits
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Lee Jones authored
This ensures userspace cannot prematurely clean-up the client before it is fully initialised which has been proven to cause issues in the past. Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by:
Lee Jones <lee.jones@linaro.org> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Ma Jun authored
Sync up header and implementation to use the same parameter names in function amdgpu_ring_init. ring_size -> max_dw, prio -> hw_prio Reviewed-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Ma Jun <Jun.Ma2@amd.com> Signed-off-by:
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Ruili Ji authored
gfx10.3.3/gfx10.3.6/gfx10.3.7 shall use 0x1580 address for GCR_GENERAL_CNTL Acked-by:
Prike Liang <Prike.Liang@amd.com> Acked-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Signed-off-by:
Ruili Ji <ruiliji2@amd.com> Signed-off-by:
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Kent Russell authored
Since unique_id is only supported in PMFW 0x3A5300 and higher, we will only be able to use it inside Smu_Metrics_V3_t, which requires PMFW 0x3A4900 and higher. Remove the unique_id/serial_number references from the v1 and v2 tables to avoid any confusion, and return 0 if metrics_v1 or metrics_v2 are used to try to get the unique_id/serial_number. Signed-off-by:
Kent Russell <kent.russell@amd.com> Reviewed-by:
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Melissa Wen authored
FPU documentation states that developers must not use DC_FP_START/END inside dml files, but use this macro to wrap calls to FPU functions in dc folder (outside dml folder). Therefore, this patch removes DC_FP_* wrappers from dml folder and wraps calls for these FPU operations outside dml, as required. Acked-by:
Melissa Wen <mwen@igalia.com> Signed-off-by:
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Melissa Wen authored
dcn10_validate_bandwidth is only used on dcn10 files, but is declared in dcn_calcs files. Rename dcn10_* to dcn_* in calcs, remove DC_FP_* wrapper inside DML folder and create an specific dcn10_validate_bandwidth in dcn10_resources that calls dcn_validate_bandwidth and properly wraps that FPU function with DC_FP_* macro. Acked-by:
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Kent Russell authored
This is being added to SMU Metrics, so add the required tie-ins in the kernel. Also create the corresponding unique_id sysfs file. v2: Add FW version check, remove SMU mutex v3: Fix style warning v4: Add MP1 IP_VERSION check to FW version check Signed-off-by:
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Kent Russell authored
This is abstracted well enough in the get_metrics_data function, so use the function Signed-off-by:
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Kent Russell authored
This will allow us to use the generic *_get_metrics_data functions for ASICs that support unique_id Signed-off-by:
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Kent Russell authored
To ease readability, use switch to set unique_id as supported for the supported IP_VERSIONs, and set it to unsupported by default for all other ASICs. This makes it easier to add IP_VERSIONs later on, and makes it obvious that it is not supported by default, instead of the current logic that assumes that it is supported unless it is not one of the specified IP_VERSIONs. v2: Rebase onto previous IP_VERSION change Signed-off-by:
Kevin Wang <KevinYang.Wang@amd.com> Signed-off-by:
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Philip Yang authored
To support multi-thread update page table. Signed-off-by:
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Christian König authored
That are bytes not pages. Signed-off-by:
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Christian König authored
Fix two incorrect kerneldocs for the recent VM code changes. v2: fix one more typo Signed-off-by:
Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by:
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Shirish S authored
[Why] comparing pwm bl values (coverted) with user brightness(converted) levels in commit_tail leads to continuous setting of backlight via dmub as they don't to match. This leads overdrive in queuing of commands to DMCU that sometimes lead to depending on load on DMCU fw: "[drm:dc_dmub_srv_wait_idle] *ERROR* Error waiting for DMUB idle: status=3" [How] Store last successfully set backlight value and compare with it instead of pwm reads which is not what we should compare with. Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Randy Dunlap authored
There is no need for this one static function to be marked as kernel-doc notation. Avoid this doc build warning: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Fixes: 110d3968 ("drm/amd/display: Add DCN3.1 OPTC") Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: Christian König <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Haowen Bai authored
The value actual_pix_clk_100Hz is dereferencing pointer pix_clk_params before pix_clk_params is being null checked. Fix this by assigning pix_clk_params->requested_pix_clk_100hz to actual_pix_clk_100Hz only if pix_clk_params is not NULL, otherwise just NULL. Signed-off-by:
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Philip Yang authored
Flush TLB needs wait for GPU update fence done. MMU notify callback to unmap range from GPUs uses unlocked GPU page table update, so add tlb_cb to unlocked update fence to increase vm->tlb_seq. Signed-off-by:
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Philip Yang authored
To fix two issues with unlocked update fence: 1. vm->last_unlocked store the latest fence without taking refcount. 2. amdgpu_vm_bo_update_mapping returns old fence, not the latest fence. Signed-off-by:
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Haowen Bai authored
The pointer edid_buf is dereferencing pointer edid before edid is being null checked. Fix this by assigning edid->raw_edid to edid_buf only if edid is not NULL, otherwise just NULL. Signed-off-by:
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Roman Li authored
[Why] On resume we do link detection for all non-MST connectors. MST is handled separately. However the condition for telling if connector is on mst branch is not enough for mst hub case. Link detection for mst branch link leads to mst topology reset. That causes assert in dc_link_allocate_mst_payload() [How] Use link type as indicator for mst link. Reviewed-by:
Wayne Lin <Wayne.Lin@amd.com> Acked-by:
Alex Hung <alex.hung@amd.com> Signed-off-by:
Roman Li <Roman.Li@amd.com> Tested-by:
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Aric Cyr authored
- [FW Promotion] Release 0.0.110.0 - Revert FEC check in validation - Update LTTPR UHBR link rate support struct - Add support for USBC connector - Add work around for AUX failure on wake - Clear optc false state when disable otg - Enable power gating before init_pipes - Remove redundant dsc power gating from init_hw - Power down hardware if timer not trigger - Correct Slice reset calculation - Enable 3-plane MPO for DCN31 - Set fec register init value - Remove SW w/a for HDCP 1.4 1A-07 failure based on ECO fix - Create underflow interrupt IRQ type Acked-by:
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Anthony Koo authored
- Revert save/restore PANEL_PWRSEQ_REF_DIV2 and other psr phy optimizations Reviewed-by:
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Martin Leung authored
why and how: causes failure on install on certain machines Reviewed-by:
George Shen <George.Shen@amd.com> Acked-by:
Martin Leung <Martin.Leung@amd.com> Tested-by:
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Michael Strauss authored
[WHY] Update field order to match DP2.0 spec SCR Reviewed-by:
Michael Strauss <michael.strauss@amd.com> Tested-by:
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Samson Tam authored
[Why] Add support for CONNECTOR_ID_USBC Reviewed-by:
Samson Tam <Samson.Tam@amd.com> Tested-by:
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Jimmy Kizito authored
[Why] When waking from low-power states, a DP sink may remain unresponsive to AUX transactions. [How] Try to toggle DPCD SET_POWER register repeatedly (up to a maximum timeout value) until DP sink becomes responsive. Reviewed-by:
Mustapha Ghaddar <Mustapha.Ghaddar@amd.com> Acked-by:
Jimmy Kizito <Jimmy.Kizito@amd.com> Tested-by:
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Charlene Liu authored
[why] when disable optc, need to clear the underflow status as well. Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
Charlene Liu <Charlene.Liu@amd.com> Tested-by:
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Roman Li authored
[Why] In init_hw() we call init_pipes() before enabling power gating. init_pipes() tries to power gate dsc but it may fail because required force-ons are not released yet. As a result with dsc config the following errors observed on resume: "REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control" [How] Move enable_power_gating_plane() before init_pipes() in init_hw() Reviewed-by:
Eric Yang <Eric.Yang2@amd.com> Acked-by:
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Roman Li authored
[Why] DSC Power down code has been moved from dcn31_init_hw into init_pipes() Need to remove it from dcn10_init_hw() as well to avoid duplicated action on dcn1.x/2.x [How] Remove DSC power down code from dcn10_init_hw() Fixes: 8fa6f4c5 ("drm/amd/display: fixed the DSC power off sequence during Driver PnP") Reviewed-by:
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Paul Hsieh authored
[WHY] In headless systems, if SetMode/Power down timer is not called, hardware will not be powered down causing HW/SW discrepancies. Powering down hardware on SetPowerState to D3 will ensure SW/HW state is accurate. [HOW] If PowerDownThread timer is not trigger but OS call SetPowerState to D3, power down hardware. Reviewed-by:
Paul Hsieh <paul.hsieh@amd.com> Tested-by:
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Chris Park authored
[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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