- 04 Nov, 2020 5 commits
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Tao Zhou authored
GFXOFF has been supported by PMFW, enable it directly in driver for dimgrey_cavefish. Signed-off-by:
Tao Zhou <tao.zhou1@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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John Clements authored
updated fw header v2 parser to set asd fw memory Reviewed-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Jinzhou.Su authored
Add flags AMD_CG_SUPPORT_GFX_FGCG for Vangogh Signed-off-by:
Jinzhou.Su <Jinzhou.Su@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Jinzhou.Su authored
1. Add FGCG for gfx10 2. Get FGCG status for pm info debugfs Signed-off-by:
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Jinzhou.Su authored
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG Signed-off-by:
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- 02 Nov, 2020 35 commits
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
Deepak R Varma <mh12gx2825@gmail.com> Signed-off-by:
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Deepak R Varma authored
When declaring pointer data, the "*" symbol should be used adjacent to the data name as per the coding style standards. This resolves following issues reported by checkpatch script: ERROR: "foo * bar" should be "foo *bar" ERROR: "foo * bar" should be "foo *bar" ERROR: "foo* bar" should be "foo *bar" ERROR: "(foo*)" should be "(foo *)" Signed-off-by:
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Alex Deucher authored
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN. Fixes: 0b08c54b ("drm/amd/display: Fix the display corruption issue on Navi10") Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch covers various .c files for this driver. Issue reported by checkpatch script. Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. The patch corrects issues for various amdgpu_*.c files for this driver. Issue reported by checkpatch script. Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by:
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Deepak R Varma authored
General code indentation and alignment changes such as replace spaces by tabs or align function arguments as per the coding style guidelines. Issue reported by checkpatch script. Signed-off-by:
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Colin Ian King authored
There is a spelling mistake in a deb_dbg message. Fix it. Reviewed-by:
Madhav Chauhan <madhav.chauhan@amd.com> Signed-off-by:
Colin Ian King <colin.king@canonical.com> Signed-off-by:
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Bernard Zhao authored
Fix typoes. Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Bernard Zhao <bernard@vivo.com> Signed-off-by:
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Alex Deucher authored
Uses the same pathes as navi. Reviewed-by:
Aaron Liu <aaron.liu@amd.com> Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Kent Russell authored
If we can't kvmalloc the pcrat_image, then we shouldn't memcpy Signed-off-by:
Kent Russell <kent.russell@amd.com> Reported-by:
kernel test robot <lkp@intel.com> Reviewed-by:
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Huang Rui authored
This patch is to fix the NULL pointer that missed set_disp_pattern_generator callback on DCN301 [ 505.054167] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 505.054176] #PF: supervisor instruction fetch in kernel mode [ 505.054181] #PF: error_code(0x0010) - not-present page [ 505.054185] PGD 0 P4D 0 [ 505.054199] Oops: 0010 [#1] SMP NOPTI [ 505.054211] CPU: 6 PID: 1306 Comm: modprobe Tainted: G W OE 5.9.0-rc5-custom #1 [ 505.054216] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS WCH0A29N_RAPV16.FD 10/29/2020 [ 505.054225] RIP: 0010:0x0 [ 505.054234] Code: Bad RIP value. [ 505.054239] RSP: 0018:ffffb88541c66f60 EFLAGS: 00010206 [ 505.054245] RAX: 0000000000000000 RBX: ffff912836070000 RCX: 0000000000000003 [ 505.054248] RDX: 000000000000000c RSI: ffff9128365001e8 RDI: ffff912836070000 [ 505.054252] RBP: ffffb88541c66fd8 R08: 0000000000000002 R09: ffffb88541c66fa2 [ 505.054265] R10: 0000000000009580 R11: 0000000000000008 R12: ffff9128365001e8 [ 505.054272] R13: 000000000000000c R14: 0000000000000438 R15: ffff9128a48bd000 [ 505.054279] FS: 00007f09f999f540(0000) GS:ffff9128b3f80000(0000) knlGS:0000000000000000 [ 505.054284] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 505.054288] CR2: ffffffffffffffd6 CR3: 00000002db98c000 CR4: 0000000000350ee0 [ 505.054291] Call Trace: [ 505.055024] dcn20_blank_pixel_data+0x148/0x260 [amdgpu] [ 505.055730] dcn20_enable_stream_timing+0x381/0x47c [amdgpu] [ 505.056641] dce110_apply_ctx_to_hw+0x337/0x577 [amdgpu] [ 505.056667] ? put_object+0x2f/0x40 [ 505.057329] dc_commit_state+0x4b3/0x9d0 [amdgpu] [ 505.058030] amdgpu_dm_atomic_commit_tail+0x405/0x1ec6 [amdgpu] [ 505.058053] ? update_stack_state+0x103/0x170 [ 505.058071] ? __module_text_address+0x12/0x60 Signed-off-by:
Changfeng <Changfeng.Zhu@amd.com> Signed-off-by:
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Alex Sierra authored
[Why] Vega20 and Arcturus asics use oss 5.0 version. [How] Replace ih ip block by navi10 for vega20 and arcturus. Signed-off-by:
Alex Sierra <alex.sierra@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Evan Quan authored
Will expand it to other ASICs after verified. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-and-tested-by:
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Likun Gao authored
Update golden setting for sienna_cichlid. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Jinzhou.Su authored
Add AMD_CG_SUPPORT_MC_MGCG and AMD_CG_SUPPORT_MC_LS Signed-off-by:
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Pratik Vishwakarma authored
[Why] Incorrect values were resulting in flash lines when MPO was enabled and system was left idle. [How] Increase min clk values only when MPO is enabled and display is active to not affect S3 power. Signed-off-by:
Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by:
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Jiansong Chen authored
Toggle on/off gfxoff during video playback to fix gpu hang. v2: change sequence to be more compatible with original code. Signed-off-by:
Jiansong Chen <Jiansong.Chen@amd.com> Reviewed-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Recout calculation does not corrrectly handle plane clip rect that extends beyond the left most border of stream source rect. This change adds handling by truncating the invisible clip rect. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
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Aric Cyr authored
Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Acked-by:
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Anthony Koo authored
[Header Changes] - Add command for retrieving PSR residency - Add command for forcing PSR static Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Bhawanpreet Lakha authored
If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Jake Wang authored
[Why] Fail and restart timing for HDCP1 retry occurs too quickly. This would cause some MST monitors to show black screen. [How] Adjusted timing of fail and restart to 200ms. Signed-off-by:
Jake Wang <haonan.wang2@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Joshua Aberback authored
[Why] Commit "Blank HUBP during pixel data blank for DCN30 v2" modifies HW behaviour during blank, which might have OS dependencies. We need to assess the impact on amdgpu_dm and only re-enable HUBP blanking when all necessary changes are understood. [How] - revert functional changes - leave architectural changes intact Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Dale Zhao authored
[Why] Customer make a request to add this WA by driver. Some MUX chips will power down with eDP 1.4 panel and lose previous supported link rates(DPCD 0x010) in customer's hybrid-GPU designs. As a result, during sleep resuming and screen turns on from idle, link training will be performed incorrectly and eDP will flicker or black screen. These MUX chips need source to read DPCD 0x010 again during LKT so that it can restore supported link rates of panel. For driver side, supported link rate set is fetched when link detection, no need to update but just read again as WA. [How] Read DPCD 0x010 again during link training for eDP 1.4. Signed-off-by:
Dale Zhao <dale.zhao@amd.com> Reviewed-by:
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Wayne Lin authored
[why] Currently, we only support calculating CRC on whole frame. We want to extend the capability to calculate CRC on specific frame area. [how] Calculate CRC on specific area once it's specified from the input parameter. Signed-off-by:
Wayne Lin <Wayne.Lin@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Victor Lu authored
[why] There is a DRM_ERROR when the dc_sink is NULL and there should not be this warning when the connector is forced. [how] Do not warn if dc_sink is NULL if the connector is forced. Signed-off-by:
Victor Lu <victorchengchi.lu@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] Prior commit "Blank HUBP during pixel data blank for DCN30" missed the call to set_disp_pattern_generator from set_crtc_test_pattern, which re-exposed the issue for which we initially blocked active-only p-state switching. [How] - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version - new hwss funciton set_disp_pattern_generator - dcn20 version just calls opp_set_disp_pattern_generator - dcn30 version implements the HUBP blank Signed-off-by:
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Alvin Lee authored
[Why] When checking if we want to disable GSL or not, we should reset flip_immediate to be the flip type of the topmost plane before looping through the other planes. [How] Set flip_immediate to be the flip type of the topmost plane before looping through the other planes. Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
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