- 13 Mar, 2020 2 commits
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Matt Roper authored
The bspec documents multiple MCR ranges; make sure they're all captured by the driver. Bspec: 13991, 52079 Fixes: 592a7c5e ("drm/i915: Extend non readable mcr range") Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Signed-off-by:
Matt Roper <matthew.d.roper@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200311162300.1838847-2-matthew.d.roper@intel.comReviewed-by:
Mika Kuoppala <mika.kuoppala@linux.intel.com>
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Chris Wilson authored
Throw in the inverse patterns to create more examples of poison to use against the LRC state. Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by:
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- 12 Mar, 2020 5 commits
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Caz Yokoyama authored
This reverts commit 36a6b5d9. The commit takes care Wa_1604544889 which was fixed on a0 stepping based on a0 replan. So no SW workaround is required on any stepping now. Reviewed-by:
Caz Yokoyama <caz.yokoyama@intel.com> Signed-off-by:
José Roberto de Souza <jose.souza@intel.com> Fixes: 36a6b5d9 ("drm/i915/tgl: Add extra hdc flush workaround") Link: https://patchwork.freedesktop.org/patch/msgid/1c751032ce79c80c5485cae315f1a9904ce07cac.1583359940.git.caz.yokoyama@intel.com
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Chris Wilson authored
During driver unload, we have many asserts that we have released our bookkeeping structs and are idle. In some cases, these struct are protected by RCU and we do not release them until after an RCU grace period. Reported-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 130a95e9 ("drm/i915/gem: Consolidate ctx->engines[] release") Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by:
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Chris Wilson authored
Switch igt_vm_isolation() to using igt_random_offset(). Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200312154708.1720-1-chris@chris-wilson.co.uk
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Chris Wilson authored
Since the relocations are no longer performed under a global struct_mutex, or any other lock, that is also held by pagefault handlers, we can relax and allow our fast path to take a fault. As we no longer need to abort the fast path for lock avoidance, we no longer need the slow path handling at all. Signed-off-by:
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Tvrtko Ursulin authored
Allow super long OpenCL workloads which cannot be preempted within the default timeout to run out of the box. v2: * Make it stick out more and apply only to RCS. (Chris) v3: * Mention platform override in kconfig. (Joonas) Signed-off-by:
Michal Mrozek <Michal.mrozek@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200312115748.29970-1-tvrtko.ursulin@linux.intel.com
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- 11 Mar, 2020 16 commits
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Chris Wilson authored
When applying the context-barrier, we only care about the current engines, as the next set of engines will be naturally after the barrier. So we can skip holding the ctx->engines_mutex while constructing the request by taking a sneaky reference to the i915_gem_engines instead. Signed-off-by:
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Chris Wilson authored
The sw-fence notify function requires to be at least 4-byte aligned so that we can use the low bits in the function pointer for internal fence flags. Make it so. References: https://gitlab.freedesktop.org/drm/intel/issues/1433 Fixes: 42fb60de ("drm/i915/gem: Don't leak non-persistent requests on changing engines") Signed-off-by:
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Kai Vehmanen authored
Gen12 hardware supports HDMI audio pixel clocks of 296.7/297Mhz and 593.4/594Mhz. Add the missing rates and add logic to ignore them if running on older hardware. Bspec: 49333 Signed-off-by:
Kai Vehmanen <kai.vehmanen@linux.intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
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Chris Wilson authored
[11057.642683] BUG: KCSAN: data-race in i915_gem_mmap [i915] / singleton_release [i915] [11057.642717] [11057.642740] write (marked) to 0xffff8881f24471a0 of 8 bytes by task 44668 on cpu 2: [11057.643162] singleton_release+0x38/0x60 [i915] [11057.643192] __fput+0x160/0x3c0 [11057.643217] ____fput+0x16/0x20 [11057.643241] task_work_run+0xba/0x100 [11057.643263] exit_to_usermode_loop+0xe4/0xf0 [11057.643286] do_syscall_64+0x27e/0x2c0 [11057.643314] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [11057.643339] [11057.643359] read to 0xffff8881f24471a0 of 8 bytes by task 44667 on cpu 3: [11057.643774] i915_gem_mmap+0x295/0x670 [i915] [11057.643802] mmap_region+0x62b/0xac0 [11057.643825] do_mmap+0x414/0x6b0 [11057.643848] vm_mmap_pgoff+0xa9/0xf0 [11057.643875] ksys_mmap_pgoff+0x1ac/0x2f0 [11057.643900] do_syscall_64+0x6e/0x2c0 [11057.643924] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
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Chris Wilson authored
Record the initial active element we use when building the next ELSP submission, so that we can compare against it latter to see if there's no change. Fixes: 44d0a9c0 ("drm/i915/execlists: Skip redundant resubmission") Signed-off-by:
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Chris Wilson authored
Avoid angering kcsan by serialising the read of the pm_events with the write in rps_disable_interrupts. [ 6268.713419] BUG: KCSAN: data-race in intel_rps_park [i915] / rps_work [i915] [ 6268.713437] [ 6268.713449] write to 0xffff8881eda8efac of 4 bytes by task 1127 on cpu 3: [ 6268.713680] intel_rps_park+0x136/0x260 [i915] [ 6268.713905] __gt_park+0x61/0xa0 [i915] [ 6268.714128] ____intel_wakeref_put_last+0x42/0x90 [i915] [ 6268.714352] __intel_wakeref_put_work+0xd3/0xf0 [i915] [ 6268.714369] process_one_work+0x3b1/0x690 [ 6268.714384] worker_thread+0x80/0x670 [ 6268.714398] kthread+0x19a/0x1e0 [ 6268.714412] ret_from_fork+0x1f/0x30 [ 6268.714423] [ 6268.714435] read to 0xffff8881eda8efac of 4 bytes by task 950 on cpu 2: [ 6268.714664] rps_work+0xc2/0x680 [i915] [ 6268.714679] process_one_work+0x3b1/0x690 [ 6268.714693] worker_thread+0x80/0x670 [ 6268.714707] kthread+0x19a/0x1e0 [ 6268.714720] ret_from_fork+0x1f/0x30 v2: Mark all reads and writes of rpm->pm_events. The flow of enabling/disabling rps is stronly ordered, so the writes and interrupt generation are also strongly ordered -- just this may not be visible to the compiler, so provide annotations. Signed-off-by:
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Chris Wilson authored
Extend i915_request_await_active() to be able to asynchronously wait on all the tracked timelines simultaneously. Signed-off-by:
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Takashi Iwai authored
Since snprintf() returns the would-be-output size instead of the actual output size, the succeeding calls may go beyond the given buffer limit. Fix it by replacing with scnprintf(). Signed-off-by:
Takashi Iwai <tiwai@suse.de> Reviewed-by:
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Wambui Karuga authored
Convert various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_overlay.c. This transformation was achieved using the following coccinelle script: @@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } Note that this converts DRM_DEBUG to drm_dbg(). Checkpatch warnings were addressed manually. References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.htmlSigned-off-by:Wambui Karuga <wambui.karugax@gmail.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ca3c14de13e308419caf33eb4bbf274f5387f1e0.1583766715.git.jani.nikula@intel.com
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Wambui Karuga authored
Converts various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_lvds.c. This transformation was done by the following coccinelle script that matches based on the existence of a drm_i915_private device: @@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were fixed manually. Signed-off-by: -
Wambui Karuga authored
Convert various uses of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_lpe_audio.c. Note that this converts DRM_DEBUG to drm_dbg(). References: https://lists.freedesktop.org/archives/dri-devel/2020-January/253381.htmlSigned-off-by:
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Wambui Karuga authored
Converts various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_hotplug.c. In some cases, this involves extracting the drm_i915_private pointer from the drm_device struct to be used in the logging macros. Signed-off-by:
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Wambui Karuga authored
Conversion instances of printk based drm logging macros to use the struct drm_device based logging macros in i915/display/intel_gmbus.c. This was done using the following coccinelle semantic patch that transforms based on the existence of an existing drm_i915_private device: @@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were addressed manually. Signed-off-by: -
Wambui Karuga authored
Convert various instances of the printk based drm logging macros to the struct drm_device based logging macros in i915/display/intel_fifo_underrun.c. This was done using the following coccinelle script: @@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } New checkpatch warnings were addressed manually. Signed-off-by: -
Wambui Karuga authored
This converts uses of the printk based drm logging macros to the struct drm_device logging macros in i915/display/intel_dsb.c. This was done using the following coccinelle script: @@ identifier fn, T; @@ fn(...,struct drm_i915_private *T,...) { <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } @@ identifier fn, T; @@ fn(...) { ... struct drm_i915_private *T = ...; <+... ( -DRM_INFO( +drm_info(&T->drm, ...) | -DRM_ERROR( +drm_err(&T->drm, ...) | -DRM_WARN( +drm_warn(&T->drm, ...) | -DRM_DEBUG( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_KMS( +drm_dbg_kms(&T->drm, ...) | -DRM_DEBUG_DRIVER( +drm_dbg(&T->drm, ...) | -DRM_DEBUG_ATOMIC( +drm_dbg_atomic(&T->drm, ...) ) ...+> } Checkpatch warnings were fixed manually. Signed-off-by: -
Tvrtko Ursulin authored
The two files have been duplicated under the gt/ subdir and since there are not apparent users looking for them at the old location lets simply remove them and duplicated code. Signed-off-by:
Andi Shyti <andi.shyti@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200310164733.26487-1-tvrtko.ursulin@linux.intel.com
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- 10 Mar, 2020 10 commits
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Chris Wilson authored
The virtual engine passes tokens back and forth to its backing physical engines. [ 57.372993] BUG: KCSAN: data-race in execlists_dequeue [i915] / virtual_submission_tasklet [i915] [ 57.373012] [ 57.373023] write to 0xffff8881f47324c0 of 4 bytes by interrupt on cpu 2: [ 57.373241] execlists_dequeue+0x6fa/0x2150 [i915] [ 57.373458] __execlists_submission_tasklet+0x48/0x60 [i915] [ 57.373677] execlists_submission_tasklet+0xd3/0x170 [i915] [ 57.373694] tasklet_action_common.isra.0+0x42/0xa0 [ 57.373709] __do_softirq+0xd7/0x2cd [ 57.373723] irq_exit+0xbe/0xe0 [ 57.373735] do_IRQ+0x51/0x100 [ 57.373748] ret_from_intr+0x0/0x1c [ 57.373963] engine_retire+0x89/0xe0 [i915] [ 57.373977] process_one_work+0x3b1/0x690 [ 57.373990] worker_thread+0x80/0x670 [ 57.374004] kthread+0x19a/0x1e0 [ 57.374017] ret_from_fork+0x1f/0x30 [ 57.374027] [ 57.374038] read to 0xffff8881f47324c0 of 4 bytes by interrupt on cpu 3: [ 57.374256] virtual_submission_tasklet+0x27/0x5a0 [i915] [ 57.374273] tasklet_action_common.isra.0+0x42/0xa0 [ 57.374288] __do_softirq+0xd7/0x2cd [ 57.374302] run_ksoftirqd+0x15/0x20 [ 57.374315] smpboot_thread_fn+0x1ab/0x300 [ 57.374329] kthread+0x19a/0x1e0 [ 57.374342] ret_from_fork+0x1f/0x30 Signed-off-by:
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Chris Wilson authored
As a virtual engine may change the rq->engine to point to the active request in flight, we need to warn the compiler that an active request's engine is volatile. [ 95.017686] write (marked) to 0xffff8881e8386b10 of 8 bytes by interrupt on cpu 2: [ 95.018123] execlists_dequeue+0x762/0x2150 [i915] [ 95.018539] __execlists_submission_tasklet+0x48/0x60 [i915] [ 95.018955] execlists_submission_tasklet+0xd3/0x170 [i915] [ 95.018986] tasklet_action_common.isra.0+0x42/0xa0 [ 95.019016] __do_softirq+0xd7/0x2cd [ 95.019043] irq_exit+0xbe/0xe0 [ 95.019068] irq_work_interrupt+0xf/0x20 [ 95.019491] i915_request_retire+0x2c5/0x670 [i915] [ 95.019937] retire_requests+0xa1/0xf0 [i915] [ 95.020348] engine_retire+0xa1/0xe0 [i915] [ 95.020376] process_one_work+0x3b1/0x690 [ 95.020403] worker_thread+0x80/0x670 [ 95.020429] kthread+0x19a/0x1e0 [ 95.020454] ret_from_fork+0x1f/0x30 [ 95.020476] [ 95.020498] read to 0xffff8881e8386b10 of 8 bytes by task 8909 on cpu 3: [ 95.020918] __i915_request_commit+0x177/0x220 [i915] [ 95.021329] i915_gem_do_execbuffer+0x38c4/0x4e50 [i915] [ 95.021750] i915_gem_execbuffer2_ioctl+0x2c3/0x580 [i915] [ 95.021784] drm_ioctl_kernel+0xe4/0x120 [ 95.021809] drm_ioctl+0x297/0x4c7 [ 95.021832] ksys_ioctl+0x89/0xb0 [ 95.021865] __x64_sys_ioctl+0x42/0x60 [ 95.021901] do_syscall_64+0x6e/0x2c0 [ 95.021927] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
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Chris Wilson authored
When being used across multiple real engines inside a virtual engine, the intel_context.inflight is updated atomically, and so we must annotate the racy read from outside the owning context. [11142.482846] BUG: KCSAN: data-race in __execlists_submission_tasklet [i915] / __execlists_submission_tasklet [i915] [11142.482867] [11142.482878] write (marked) to 0xffff8881f257b5e0 of 8 bytes by interrupt on cpu 2: [11142.483107] __execlists_submission_tasklet+0x1d33/0x2120 [i915] [11142.483336] execlists_submission_tasklet+0xd3/0x170 [i915] [11142.483355] tasklet_action_common.isra.0+0x42/0xa0 [11142.483371] __do_softirq+0xd7/0x2cd [11142.483384] irq_exit+0xbe/0xe0 [11142.483401] do_IRQ+0x51/0x100 [11142.483424] ret_from_intr+0x0/0x1c [11142.483446] do_idle+0x133/0x1f0 [11142.483465] cpu_startup_entry+0x14/0x16 [11142.483483] start_secondary+0x120/0x180 [11142.483498] secondary_startup_64+0xa4/0xb0 [11142.483512] [11142.483528] read to 0xffff8881f257b5e0 of 8 bytes by interrupt on cpu 1: [11142.483755] __execlists_submission_tasklet+0x14e/0x2120 [i915] [11142.483981] execlists_submission_tasklet+0xd3/0x170 [i915] [11142.483999] tasklet_action_common.isra.0+0x42/0xa0 [11142.484014] __do_softirq+0xd7/0x2cd [11142.484028] do_softirq_own_stack+0x2a/0x40 [11142.484046] do_softirq.part.0+0x26/0x30 [11142.484071] __local_bh_enable_ip+0x46/0x50 [11142.484299] i915_gem_do_execbuffer+0x39c1/0x4e50 [i915] [11142.484528] i915_gem_execbuffer2_ioctl+0x2c3/0x580 [i915] [11142.484546] drm_ioctl_kernel+0xe4/0x120 [11142.484559] drm_ioctl+0x297/0x4c7 [11142.484572] ksys_ioctl+0x89/0xb0 [11142.484586] __x64_sys_ioctl+0x42/0x60 [11142.484610] do_syscall_64+0x6e/0x2c0 [11142.484627] entry_SYSCALL_64_after_hwframe+0x44/0xa9 Signed-off-by:
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Chris Wilson authored
Skip useless priority bumping on adding a new dependency by making sure that we do update the priority if we would have rescheduled the active cotnext. Signed-off-by:
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Chris Wilson authored
Since the semaphore fence may be signaled from inside an interrupt handler from inside a request holding its request->lock, we cannot then enter into the engine->active.lock for processing the semaphore priority bump as we may traverse our call tree and end up on another held request. CPU 0: [ 2243.218864] _raw_spin_lock_irqsave+0x9a/0xb0 [ 2243.218867] i915_schedule_bump_priority+0x49/0x80 [i915] [ 2243.218869] semaphore_notify+0x6d/0x98 [i915] [ 2243.218871] __i915_sw_fence_complete+0x61/0x420 [i915] [ 2243.218874] ? kmem_cache_free+0x211/0x290 [ 2243.218876] i915_sw_fence_complete+0x58/0x80 [i915] [ 2243.218879] dma_i915_sw_fence_wake+0x3e/0x80 [i915] [ 2243.218881] signal_irq_work+0x571/0x690 [i915] [ 2243.218883] irq_work_run_list+0xd7/0x120 [ 2243.218885] irq_work_run+0x1d/0x50 [ 2243.218887] smp_irq_work_interrupt+0x21/0x30 [ 2243.218889] irq_work_interrupt+0xf/0x20 CPU 1: [ 2242.173107] _raw_spin_lock+0x8f/0xa0 [ 2242.173110] __i915_request_submit+0x64/0x4a0 [i915] [ 2242.173112] __execlists_submission_tasklet+0x8ee/0x2120 [i915] [ 2242.173114] ? i915_sched_lookup_priolist+0x1e3/0x2b0 [i915] [ 2242.173117] execlists_submit_request+0x2e8/0x2f0 [i915] [ 2242.173119] submit_notify+0x8f/0xc0 [i915] [ 2242.173121] __i915_sw_fence_complete+0x61/0x420 [i915] [ 2242.173124] ? _raw_spin_unlock_irqrestore+0x39/0x40 [ 2242.173137] i915_sw_fence_complete+0x58/0x80 [i915] [ 2242.173140] i915_sw_fence_commit+0x16/0x20 [i915] Closes: https://gitlab.freedesktop.org/drm/intel/issues/1318 Fixes: b7404c7e ("drm/i915: Bump ready tasks ahead of busywaits") Signed-off-by:
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https://github.com/intel/gvt-linuxRodrigo Vivi authored
gvt-next-2020-03-10 - Fix CFL dmabuf display after vfio edid enabling (Tina) - Clean up scan non-priv batch debugfs entry (Chris) - Use intel engines initialized in gvt, cleanup previous ring id (Chris) - Use intel_gt instead (Chris) Signed-off-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> From: Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200310081928.GG28483@zhen-hp.sh.intel.com
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Radhakrishna Sripada authored
Platforms without fences don't have FBC host tracking and those registers are marked as reserved in those platforms. v2: checking num_fences to write to FBC fence registers (Ville) Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Radhakrishna Sripada <radhakrishna.sripada@intel.com> Signed-off-by:
Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by:
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José Roberto de Souza authored
Most of the kms_frontbuffer_tracking tests disables the feature being tested, draw, get the CRC then enable the feature, draw again, get the CRC and check if it matches. Some times it is able to do that with a fastset, so intel_pre_plane_update() is executed but intel_fbc_can_flip_nuke() was not checking if FBC is now enabled in this CRTC leaving FBC active and causing the warning bellow in __intel_fbc_disable() [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-pri-indfb-multidraw Setting dangerous option enable_fbc - tainting kernel i915 0000:00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR debug to f i915 0000:00:02.0: [drm:intel_psr_debug_set [i915]] Invalid debug mask f i915 0000:00:02.0: [drm:i915_edp_psr_debug_set [i915]] Setting PSR debug to 1 i915 0000:00:02.0: [drm:intel_atomic_check [i915]] [CONNECTOR:215:eDP-1] Limiting display bpp to 24 instead of EDID bpp 24, requested bpp 36, max platform bpp 36 [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max rate 270000 max bpp 24 pixel clock 138120KHz [drm:intel_dp_compute_config [i915]] Force DSC en = 0 [drm:intel_dp_compute_config [i915]] DP lane count 2 clock 270000 bpp 24 [drm:intel_dp_compute_config [i915]] DP link rate required 414360 available 540000 i915 0000:00:02.0: [drm:intel_atomic_check [i915]] hw max bpp: 24, pipe bpp: 24, dithering: 0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [CRTC:91:pipe A] enable: yes [fastset] i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] active: yes, output_types: EDP (0x100), output format: RGB i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6436858, gmch_n: 8388608, link_m: 268202, link_n: 524288, tu: 64 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0, infoframes enabled: 0x0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] requested mode: [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] adjusted mode: [drm:drm_mode_debug_printmodeline] Modeline "1920x1080": 60 138120 1920 1968 2018 2052 1080 1084 1086 1122 0x48 0xa [drm:intel_dump_pipe_config [i915]] crtc timings: 138120 1920 1968 2018 2052 1080 1084 1086 1122, type: 0x48 flags: 0xa i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138120 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] linetime: 119, ips linetime: 0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled, force thru: no i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0 [drm:icl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x1c001a5, cfgcr1: 0x8b, mg_refclkin_ctl: 0x0, hg_clktop2_coreclkctl1: 0x0, mg_clktop2_hsclkctl: 0x0, mg_pll_div0: 0x0, mg_pll_div2: 0x0, mg_pll_lf: 0x0, mg_pll_frac_lock: 0x0, mg_pll_ssc: 0x0, mg_pll_bias: 0x0, mg_pll_tdc_coldst_bias: 0x0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] csc_mode: 0x0 gamma_mode: 0x0 gamma_enable: 0 csc_enable: 0 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] MST master transcoder: <invalid> i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 1A] fb: [FB:262] 1920x1080 format = XR24 little-endian (0x34325258), visible: yes i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] rotation: 0x1, scaler: -1 i915 0000:00:02.0: [drm:intel_dump_pipe_config [i915]] src: 1920.000000x1080.000000+0.000000+0.000000 dst: 1920x1080+0+0 i915 0000:00:02.0: [drm:intel_psr_disable_locked [i915]] Disabling PSR1 i915 0000:00:02.0: [drm:intel_ddi_update_pipe [i915]] Panel doesn't support DRRS ------------[ cut here ]------------ i915 0000:00:02.0: drm_WARN_ON(fbc->active) WARNING: CPU: 4 PID: 1175 at drivers/gpu/drm/i915/display/intel_fbc.c:973 __intel_fbc_disable+0xa5/0x130 [i915] Modules linked in: snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic i915 mei_hdcp x86_pkg_temp_thermal coretemp crct10dif_pclmul snd_hda_intel crc32_pclmul snd_intel_dspcfg snd_hda_codec ghash_clmulni_intel snd_hwdep snd_hda_core cdc_ether e1000e usbnet mii snd_pcm ptp mei_me pps_core mei thunderbolt intel_lpss_pci prime_numbers CPU: 4 PID: 1175 Comm: kms_frontbuffer Tainted: G U 5.5.0-CI-Trybot_5651+ #1 Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U DDR4 SODIMM PD RVP TLC, BIOS ICLSFWR1.R00.3234.A01.1906141750 06/14/2019 RIP: 0010:__intel_fbc_disable+0xa5/0x130 [i915] Code: 8b 67 50 4d 85 e4 0f 84 8f 00 00 00 e8 44 33 30 e1 48 c7 c1 72 f6 4c a0 4c 89 e2 48 89 c6 48 c7 c7 42 f6 4c a0 e8 0b 9d ce e0 <0f> 0b eb 90 48 8b 7b 18 4c 8b 67 50 4d 85 e4 74 6d e8 15 33 30 e1 RSP: 0018:ffffc90000613b68 EFLAGS: 00010282 RAX: 0000000000000000 RBX: ffff8884799d0000 RCX: 0000000000000006 RDX: 0000000000001905 RSI: ffff888495dac970 RDI: ffffffff823731a1 RBP: ffff88847c05d000 R08: ffff888495dac970 R09: 0000000000000000 R10: ffffc90000613b88 R11: 0000000000000000 R12: ffff88849bba7e40 R13: ffff8884799d0000 R14: ffff888498564000 R15: 0000000000000000 FS: 00007f8157f08300(0000) GS:ffff8884a0000000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ffdbfea2eb8 CR3: 000000049d1cc001 CR4: 0000000000760ee0 PKRU: 55555554 Call Trace: intel_fbc_disable+0x4a/0x50 [i915] intel_update_crtc+0x12c/0x1d0 [i915] skl_commit_modeset_enables+0x14d/0x600 [i915] intel_atomic_commit_tail+0x30d/0x1480 [i915] ? queue_work_on+0x31/0x70 ? intel_atomic_commit_ready+0x3f/0x48 [i915] ? __i915_sw_fence_complete+0x1a0/0x250 [i915] intel_atomic_commit+0x312/0x390 [i915] intel_psr_fastset_force+0x119/0x150 [i915] i915_edp_psr_debug_set+0x53/0x70 [i915] simple_attr_write+0xb0/0xd0 full_proxy_write+0x51/0x80 vfs_write+0xb9/0x1d0 ksys_write+0x9f/0xe0 do_syscall_64+0x4f/0x220 entry_SYSCALL_64_after_hwframe+0x49/0xbe RIP: 0033:0x7f8157240281 Code: c3 0f 1f 84 00 00 00 00 00 48 8b 05 59 8d 20 00 c3 0f 1f 84 00 00 00 00 00 8b 05 8a d1 20 00 85 c0 75 16 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 57 f3 c3 0f 1f 44 00 00 41 54 55 49 89 d4 53 RSP: 002b:00007ffdbfea59d8 EFLAGS: 00000246 ORIG_RAX: 0000000000000001 RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007f8157240281 RDX: 0000000000000003 RSI: 00007f8157901152 RDI: 0000000000000008 RBP: 0000000000000003 R08: 0000000000000000 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007f8157901152 R13: 0000000000000008 R14: 00005589d298dce0 R15: 0000000000000000 irq event stamp: 55208 hardirqs last enabled at (55207): [<ffffffff8112f3fc>] vprintk_emit+0xcc/0x330 hardirqs last disabled at (55208): [<ffffffff81001ca0>] trace_hardirqs_off_thunk+0x1a/0x1c softirqs last enabled at (54926): [<ffffffff81e00385>] __do_softirq+0x385/0x47f softirqs last disabled at (54915): [<ffffffff810ba15a>] irq_exit+0xba/0xc0 ---[ end trace afa50c52e5a512bb ]--- [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A i915 0000:00:02.0: [drm:verify_connector_state [i915]] [CONNECTOR:215:eDP-1] i915 0000:00:02.0: [drm:intel_atomic_commit_tail [i915]] [CRTC:91:pipe A] [drm:intel_ddi_get_config [i915]] [ENCODER:214:DDI A] Fec status: 0 i915 0000:00:02.0: [drm:verify_single_dpll_state.isra.150 [i915]] DPLL 0 v2: using intel_fbc_can_enable() instead of crtc_state->enable_fbc (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
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Lyude Paul authored
i915 can enable aux device nodes for DP MST by calling drm_dp_mst_connector_late_register()/ drm_dp_mst_connector_early_unregister(), so let's hook that up. Changes since v1: * Call intel_connector_register/unregister() from intel_dp_mst_connector_late_register/unregister() so we don't lose error injection - Ville Syrjälä Changes since v2: * Don't forget to clean up if intel_connector_register() fails - Ville Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: "Lee, Shawn C" <shawn.c.lee@intel.com> Signed-off-by:
Lyude Paul <lyude@redhat.com> Reviewed-by:
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Chris Wilson authored
Always wait on the start of the signaler request to reduce the problem of dequeueing the bonded pair too early -- we want both payloads to start at the same time, with no latency, and yet still allow others to make full use of the slack in the system. This reduce the amount of time we spend waiting on the semaphore used to synchronise the start of the bonded payload. Signed-off-by:
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- 09 Mar, 2020 7 commits
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Chris Wilson authored
[ 206.875637] BUG: KCSAN: data-race in __i915_schedule+0x7fc/0x930 [i915] [ 206.875654] [ 206.875666] race at unknown origin, with read to 0xffff8881f7644480 of 8 bytes by task 703 on cpu 3: [ 206.875901] __i915_schedule+0x7fc/0x930 [i915] [ 206.876130] __bump_priority+0x63/0x80 [i915] [ 206.876361] __i915_sched_node_add_dependency+0x258/0x300 [i915] [ 206.876593] i915_sched_node_add_dependency+0x50/0xa0 [i915] [ 206.876824] i915_request_await_dma_fence+0x1da/0x530 [i915] [ 206.877057] i915_request_await_object+0x2fe/0x470 [i915] [ 206.877287] i915_gem_do_execbuffer+0x45dc/0x4c20 [i915] [ 206.877517] i915_gem_execbuffer2_ioctl+0x2c3/0x580 [i915] [ 206.877535] drm_ioctl_kernel+0xe4/0x120 [ 206.877549] drm_ioctl+0x297/0x4c7 [ 206.877563] ksys_ioctl+0x89/0xb0 [ 206.877577] __x64_sys_ioctl+0x42/0x60 [ 206.877591] do_syscall_64+0x6e/0x2c0 [ 206.877606] entry_SYSCALL_64_after_hwframe+0x44/0xa9 v2: Be safe and include mb References: https://gitlab.freedesktop.org/drm/intel/issues/1318Signed-off-by:
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Ville Syrjälä authored
gmbus/aux may be clocked by cdclk, thus we should make sure no transfers are ongoing while the cdclk frequency is being changed. We do that by simply grabbing all the gmbus/aux mutexes. No one else should be holding any more than one of those at a time so the lock ordering here shouldn't matter. v2: Use mutex_lock_nest_lock() (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ville Syrjälä authored
The low level read_lut() functions don't need the entire crtc state as they know exactly what they're reading. Just need to pass in the crtc to get at the pipe. This now neatly mirrors the load_lut() direction. Signed-off-by:
Swati Sharma <swati2.sharma@intel.com>
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Ville Syrjälä authored
PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can represent a value of 1.0 when the maximum we can store in the software LUT is 0.ffff. Clamp the value so that it gets saturated to the max the uapi supports. Signed-off-by:
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Ville Syrjälä authored
Extract all the 'hw value -> LUT entry' stuff into small helpers to make the main 'read out the entire LUT' loop less bogged down by such mundane details. Signed-off-by:
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Ville Syrjälä authored
A variable called 'i' having an unsigned type is just looking for trouble, and using a sized type generally makes no sense either. Change all of them to just plain old int. And do the same for some 'lut_size' variables which generally provide the loop end codition for 'i'. Signed-off-by:
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Ville Syrjälä authored
chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so let's rename it to reflect that fact. This also mirrors the other direction's chv_load_cgm_gamma(). Signed-off-by:
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