- 27 May, 2024 40 commits
-
-
Adam Skladowski authored
Add the nodes describing the apps and gpu iommu and its context banks that are found on msm8976 SoCs. Signed-off-by:
Adam Skladowski <a39.skl@gmail.com> Link: https://lore.kernel.org/r/20240508163455.8757-2-a39.skl@gmail.comSigned-off-by:
Bjorn Andersson <andersson@kernel.org>
-
Luca Weiss authored
Add the different services found on APR on some devices with SC7280 SoC. Additionally add an empty sound node in the root node as is seen on other SoC dtsi files so device dt's can easily use that. Signed-off-by:
Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20240510-sc7280-apr-v1-1-e9eabda05f85@fairphone.comSigned-off-by:
-
Dmitry Baryshkov authored
Follow other Qualcomm platforms and rename pm8150b_role_switch_in to pm8150_hs_in. Corresponding port is described as HS port rather than role switching. Signed-off-by:
Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240512-typec-fix-sm8250-v4-9-ad153c747a97@linaro.orgSigned-off-by:
-
Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
-
Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
-
Dmitry Baryshkov authored
Follow example of other platforms. Rename HS graph nodes to contain 'dwc3_hs' and link SS lanes from DWC3 controllers to QMP PHYs. Signed-off-by:
-
Dmitry Baryshkov authored
To follow other Qualcomm platforms, update QMP USB+DP PHYs to use newer bindings rather than old bindings which had PHYs as subdevices. Signed-off-by:
-
Dmitry Baryshkov authored
The SuperSpeed signals originate from the DWC3 host controller and then are routed through the Combo QMP PHY, where they are multiplexed with the DisplayPort signals. Add corresponding OF graph link. Reported-by:
-
Dmitry Baryshkov authored
The OF graph should describe physical signals. There is no 'role switch' signal between Type-C connector and the DWC3 USB controller. Rename endpoints to mention USB HS signal instead (this follows the example lead by other plaforms, including QRB2210 RB1, QRB4210 RB2 and all PMIC GLINK platforms). Reviewed-by:
Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by:
-
Dmitry Baryshkov authored
Correct the clocks being used by the display clock controller on the SC8180X platform (to match the schema): - Drop the sleep clock - Add DSI clocks - Reorder eDP / DP clocks This changes the order of clocks, however it should be noted that the clock list was neither correct nor followed the schema beforehand. Signed-off-by:
-
Marc Gonzalez authored
15 qcom platform DTSI files define an adreno_smmu node. msm8998 is the only one with adreno_smmu disabled by default. There's no reason why this SMMU should be disabled by default, it doesn't need any further configuration. Bring msm8998 in line with the 14 other platforms. This fixes GPU init failing with ENODEV: msm_dpu c901000.display-controller: failed to load adreno gpu msm_dpu c901000.display-controller: failed to bind 5000000.gpu (ops a3xx_ops): -19 Fixes: 87cd46d6 ("Configure Adreno GPU and related IOMMU") Signed-off-by:
Marc Gonzalez <mgonzalez@freebox.fr> Reviewed-by:
Marijn Suijten <marijn.suijten@somainline.org> Reviewed-by:
Jeffrey Hugo <quic_jhugo@quicinc.com> Link: https://lore.kernel.org/r/be51d1a4-e8fc-48d1-9afb-a42b1d6ca478@freebox.frSigned-off-by:
-
Rohit Agarwal authored
Add devicetree node for I2C and SPI busses in SDX75. Signed-off-by:
Rohit Agarwal <rohiagar@qti.qualcomm.com> Link: https://lore.kernel.org/r/20240517100423.2006022-3-quic_rohiagar@quicinc.comSigned-off-by:
-
Jie Gan authored
Add following coresight components on SA8775p, TMC/ETF, TPDM, dynamic Funnel, TPDA and ETM. Signed-off-by:
Jie Gan <quic_jiegan@quicinc.com> Link: https://lore.kernel.org/r/20240521011946.3148712-2-quic_jiegan@quicinc.comSigned-off-by:
-
Neil Armstrong authored
This add initial support for the Lenovo Smart Tab M10 (WiFi) (model tbx605f) which is a 10.1" tablet by Lenovo based on the SDM450 SoC. It has a 10.1" LCP touch panel, SDCard slot, Volume+Power buttons, USB-C port amd front-facing camera (not supported). The proper LCP Panel support will be added later, for now using the simeple-framebuffer with the bootloader-initialized video memory. Signed-off-by:
Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240523-topic-sdm450-upstream-tbx605f-v1-3-e52b89133226@linaro.orgSigned-off-by:
-
Naina Mehta authored
Enable SDHCI on sdx75-idp to support SD card. Also add the required regulators. Signed-off-by:
Naina Mehta <quic_nainmeht@quicinc.com> Link: https://lore.kernel.org/r/20240523120337.9530-4-quic_nainmeht@quicinc.comSigned-off-by:
-
Naina Mehta authored
Add sdhc node for SDX75 SoC to support SD card. Also add pins required for SDHCI. Signed-off-by:
-
Richard Acayan authored
The shared memory region is used for information about the SoC and communication with remote processors. Add the smem region for SDM670. Signed-off-by:
Richard Acayan <mailingradian@gmail.com> Link: https://lore.kernel.org/r/20240524012023.318965-8-mailingradian@gmail.comSigned-off-by:
-
Dmitry Baryshkov authored
Add calibration variant that is used by the board data for the laptop: bus=snoc,qmi-board-id=ff,qmi-chip-id=30214,variant=Lenovo_C630 Signed-off-by:
-
Dmitry Baryshkov authored
Specify firmware path for the IPA network controller on the Lenovo Yoga C630 laptop. Without this property IPA tries to load firmware from the default location, which likely will fail. Fixes: 2e01e0c2 ("arm64: dts: qcom: sdm850-yoga: Enable IPA") Signed-off-by:
-
Mukesh Ojha authored
Enable download mode setting for sm8650 which can help collect ramdump for this SoC. Signed-off-by:
Mukesh Ojha <quic_mojha@quicinc.com> Reviewed-by:
Elliot Berman <quic_eberman@quicinc.com> Reviewed-by:
Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/1715888133-2810-1-git-send-email-quic_mojha@quicinc.comSigned-off-by:
-
Komal Bajaj authored
Enable both USB controllers and associated hsphy and qmp phy nodes on QRU1000 IDP. Co-developed-by:
Amrit Anand <quic_amrianan@quicinc.com> Signed-off-by:
Komal Bajaj <quic_kbajaj@quicinc.com> Link: https://lore.kernel.org/r/20240502090326.21489-4-quic_kbajaj@quicinc.comSigned-off-by:
-
Komal Bajaj authored
Enable both USB controllers and associated hsphy and qmp phy nodes on QDU1000 IDP. Co-developed-by:
-
Komal Bajaj authored
Add devicetree nodes for enabling USB3 controller, Qcom QMP PHY and SNPS HS PHY on QDU1000/QRU1000 SoCs. Also add required pins for USB, so that the interface can work reliably. Co-developed-by:
-
Dmitry Baryshkov authored
The USB PHYs don't use extcon connectors, drop the extcon property from the hsusb_phy1 node. Fixes: 46680fe9 ("arm64: dts: qcom: msm8996: Add support for the Xiaomi MSM8996 platform") Cc: Yassine Oudjana <y.oudjana@protonmail.com> Signed-off-by:
-
Dmitry Baryshkov authored
On the IFC6560 one of the USB PHY supplies is the L10A power supply. However this regulator also supplies VDDA_APC1_CS, VDD_PLL2 and VDD_P11 consumers. Touching the supply causes the board to be reset. Document the supply as a fixed always-on regulator. Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 07fa917a ("arm64: dts: qcom: sm8450: add ufs nodes") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 59c7cf81 ("arm64: dts: qcom: sm8350: Add UFS nodes") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: b7e2fba0 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 5a814af5 ("arm64: dts: qcom: sm6350: Add UFS nodes") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 97e563bf ("arm64: dts: qcom: sm6115: Add basic soc dtsi") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: cc16687f ("arm64: dts: qcom: sdm845: add UFS controller") Signed-off-by:
-
Dmitry Baryshkov authored
The UFS PHY is powered on via the UFS_PHY_GDSC power domain. Add corresponding power-domain the the PHY node. Fixes: 8575f197 ("arm64: dts: qcom: Introduce the SC8180x platform") Signed-off-by:
-
Dmitry Baryshkov authored
The DT schema doesn't have a fallback compatible for qcom,sc7180-qmp-ufs-phy. Drop it from the dtsi too. Fixes: 858536d9 ("arm64: dts: qcom: sc7180: Add UFS nodes") Signed-off-by:
Douglas Anderson <dianders@chromium.org> Link: https://lore.kernel.org/r/20240501-qcom-phy-fixes-v1-4-f1fd15c33fb3@linaro.orgSigned-off-by:
-
Mrinmay Sarkar authored
Add ep pcie dtsi node for pcie1 controller found on sa8775p platform. It supports gen4 and x4 link width. Limiting the speed to Gen3 due to stability issue with Gen4. Signed-off-by:
Mrinmay Sarkar <quic_msarkar@quicinc.com> Link: https://lore.kernel.org/r/1714494089-7917-3-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
-
Mrinmay Sarkar authored
Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by:
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/1714492540-15419-4-git-send-email-quic_msarkar@quicinc.comSigned-off-by:
-
Krzysztof Kozlowski authored
Node names should not have vendor prefixes. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by:
-
Kaushal Kumar authored
Add SMP2P node for the SDX75 platform to communicate with the modem. Signed-off-by:
Kaushal Kumar <quic_kaushalk@quicinc.com> Link: https://lore.kernel.org/r/20240426112837.17478-1-quic_kaushalk@quicinc.comSigned-off-by:
-
Rohit Agarwal authored
Add AOSS channel devicetree node for Qcom's SDX75 SoC. Signed-off-by:
Rohit Agarwal <quic_rohiagar@quicinc.com> Link: https://lore.kernel.org/r/20240426055326.3141727-7-quic_rohiagar@quicinc.comSigned-off-by:
-
Rohit Agarwal authored
Add TCSR register space devicetree node for accessing different status registers. Signed-off-by:
-
Rohit Agarwal authored
Add IPCC devicetree node to Qcom's SDX75 platform. Signed-off-by:
-
