- 03 Feb, 2023 1 commit
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Arnd Bergmann authored
Merge tag 'v6.2-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers Introduce MediaTek regulator coupler driver to ensure that the SRAM voltage in par with the GPU voltage. This allows for a stable use of the GPU. mtk-mutex: - add support for MT8188 vdosys0 path - allow it to be build as module - add support for MT8195 vdosys1 path mmsys: - add MT8188 vdosys0 path - allow to be build as a module - add MT8195 vdosys1 path - add support for CMDQ - allow for up to 64 reset bits - add supprot for the MT8195 vppsys[0,1] pathes pm-domains: - keep power for the MT8186 ADSP on by default - add support for MT8188 - add support for buck isolation needed in specific pm-domains for MT8188 and MT8192 mtk-svs: - enable IRQ later to allow using kexec - several improvments on the code base - fix modalias pmic wrapper: - convert binding to yaml. As this is thightly coupled to the MT6357 PMIC, I took patches regarding it as well. * tag 'v6.2-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (41 commits) soc: mediatek: mtk-svs: add missing MODULE_DEVICE_TABLE soc: mediatek: mtk-devapc: Switch to devm_clk_get_enabled() soc: mtk-svs: mt8183: refactor o_slope calculation soc: mediatek: mtk-svs: delete superfluous platform data entries soc: mediatek: mtk-svs: move svs_platform_probe into probe soc: mediatek: mtk-svs: improve readability of platform_probe soc: mediatek: mtk-svs: clean up platform probing soc: mediatek: mtk-svs: keep svs alive if CONFIG_DEBUG_FS not supported soc: mediatek: mtk-svs: Use pm_runtime_resume_and_get() in svs_init01() soc: mediatek: mtk-svs: reset svs when svs_resume() fail soc: mediatek: mtk-svs: restore default voltages when svs_init02() fail soc: mediatek: mmsys: add support for MT8195 VPPSYS dt-bindings: arm: mediatek: mmsys: Add support for MT8195 VPPSYS soc: mediatek: Introduce mediatek-regulator-coupler driver soc: mediatek: mtk-svs: Enable the IRQ later soc: mediatek: add mtk-mutex support for mt8195 vdosys1 soc: mediatek: add mtk-mutex component - dp_intf1 soc: mediatek: mmsys: add reset control for MT8195 vdosys1 soc: mediatek: mmsys: add mmsys for support 64 reset bits soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1 ... Link: https://lore.kernel.org/r/396d51fc-81f3-4a2b-d7a7-b966bfe3002a@gmail.comSigned-off-by:
Arnd Bergmann <arnd@arndb.de>
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- 01 Feb, 2023 4 commits
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https://github.com/Xilinx/linux-xlnxArnd Bergmann authored
arm64: ZynqMP SoC changes for v6.3 Firmware changes - fix memory leak in error path inside notification code - trivial comment cleanup - add workaround for SD tap delay programming with old PMUFW * tag 'zynqmp-soc-for-v6.3' of https://github.com/Xilinx/linux-xlnx: firmware: xilinx: Clear IOCTL_SET_SD_TAPDELAY using PM_MMIO_WRITE firmware: xilinx: Remove kernel-doc marking in the code driver: soc: xilinx: fix memory leak in xlnx_add_cb_for_notify_event() Link: https://lore.kernel.org/r/42be5129-3ca2-ddbc-ac3b-6448245b61c2@monstr.euSigned-off-by:
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Jonathan Neuschäfer authored
Add a SoC information driver for Nuvoton WPCM450 SoCs. It provides information such as the SoC revision. Usage example: # grep . /sys/devices/soc0/* /sys/devices/soc0/family:Nuvoton NPCM /sys/devices/soc0/revision:A3 /sys/devices/soc0/soc_id:WPCM450 Signed-off-by:
Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by:
Joel Stanley <joel@jms.id.au> Reviewed-by:
Paul Menzel <pmenzel@molgen.mpg.de> Link: https://lore.kernel.org/r/20221031223926.241641-1-j.neuschaefer@gmx.netSigned-off-by:
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Zeng Heng authored
This patch adds missing MODULE_DEVICE_TABLE definition which generates correct modalias for automatic loading of this driver when it is built as an external module. Signed-off-by:
Zeng Heng <zengheng4@huawei.com> Link: https://lore.kernel.org/r/20220928151346.1942977-1-zengheng4@huawei.comSigned-off-by:
Matthias Brugger <matthias.bgg@gmail.com>
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AngeloGioacchino Del Regno authored
This driver does exactly devm_clk_get() and clk_prepare_enable() right after, which is exactly what devm_clk_get_enabled() does: clean that up by switching to the latter. This commit brings no functional changes. Signed-off-by:
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221006110935.59695-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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- 31 Jan, 2023 9 commits
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Roger Lu authored
The o_slope value is dependent of the o_slope_sign, refactor code to get rid of unnecessary if constructs. Signed-off-by:
Roger Lu <roger.lu@mediatek.com> Reviewed-by:
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Matthias Brugger authored
The platform name and efuse parsing function pointer are only used while probing the device. Use them from the svs_platform_data struct instead. Reviewed-by:
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Matthias Brugger authored
Moving svs_platform_probe into driver probe function will allow us to reduce svs_platform members. This will be done in a follow-up patch. Reviewed-by:
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Matthias Brugger authored
If a compatible misses a match data entry, then something is wrong in the development phase, we don't need to check for that at runtime. Reviewed-by:
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Matthias Brugger authored
We only ever call the SoC specific probe function from svs_platform_probe. No need to carry that function in a global datastructure around. Reviewed-by:
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Roger Lu authored
Some projects might not support CONFIG_DEBUG_FS but still needs svs to be alive. Therefore, enclose debug cmd codes with CONFIG_DEBUG_FS to make sure svs can be alive when CONFIG_DEBUG_FS not supported. Signed-off-by:
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Shang XiaoJing authored
svs_init01() calls pm_runtime_get_sync() and added fail path as svs_init01_finish to put usage_counter. However, pm_runtime_get_sync() will increment usage_counter even it failed. Fix it by replacing it with pm_runtime_resume_and_get() to keep usage counter balanced. Fixes: 681a02e9 ("soc: mediatek: SVS: introduce MTK SVS engine") Signed-off-by:
Shang XiaoJing <shangxiaojing@huawei.com> Signed-off-by:
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Roger Lu authored
Add svs reset when svs_resume() fail. Fixes: a825d72f ("soc: mediatek: fix missing clk_disable_unprepare() on err in svs_resume()") Signed-off-by:
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Roger Lu authored
If svs init02 fail, it means we cannot rely on svs bank voltages anymore. We need to disable svs function and restore DVFS opp voltages back to the default voltages for making sure we have enough DVFS voltages. Fixes: 681a02e9 ("soc: mediatek: SVS: introduce MTK SVS engine") Fixes: 0bbb09b2 ("soc: mediatek: SVS: add mt8192 SVS GPU driver") Signed-off-by:
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- 30 Jan, 2023 11 commits
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Arnd Bergmann authored
Selecting CONFIG_PM_GENERIC_DOMAINS without CONFIG_PM leads to a build failure: WARNING: unmet direct dependencies detected for PM_GENERIC_DOMAINS Depends on [n]: PM [=n] Selected by [y]: - SUN20I_PPU [=y] && (ARCH_SUNXI [=n] || COMPILE_TEST [=y]) drivers/base/power/domain_governor.c: In function 'default_suspend_ok': drivers/base/power/domain_governor.c:85:24: error: 'struct dev_pm_info' has no member named 'ignore_children' 85 | if (!dev->power.ignore_children) | ^ drivers/base/power/domain.c: In function 'genpd_queue_power_off_work': drivers/base/power/domain.c:657:20: error: 'pm_wq' undeclared (first use in this function) 657 | queue_work(pm_wq, &genpd->power_off_work); | ^~~~~ Unfortunately platforms are inconsistent between using 'select PM' and 'depends on PM' here. CONFIG_PM is a user-visible symbol, so in principle we should be using 'depends on', but on the other hand using 'select' here is more common among drivers/soc. Go with the majority for now, as this has a smaller risk of introducing circular dependencies. We may need to clean this up for consistency later. Fixes: 0e30ca5a ("soc: sunxi: Add Allwinner D1 PPU driver") Acked-by:Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by:
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Arnd Bergmann authored
Merge tag 'amlogic-drivers-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers Amlogic Drivers changes for v6.3: - Merge of immutable bindings branch with Reset & power domain binding - Addition of NNA power domain for A311D SoC - meson_sm.txt conversionto dt-schema - mark amlogic,meson-gx-pwrc bindings as deprecated - fix of meson_sm driver by using NULL instead of 0 * tag 'amlogic-drivers-for-v6.3' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: firmware: meson_sm: stop using 0 as NULL pointer dt-bindings: power: amlogic,meson-gx-pwrc: mark bindings as deprecated dt-bindings: firmware: convert meson_sm.txt to dt-schema soc: amlogic: meson-pwrc: Add NNA power domain for A311D dt-bindings: power: Add G12A NNA power domain dt-bindings: reset: meson-g12a: Add missing NNA reset Link: https://lore.kernel.org/r/ec9552d8-96df-a677-ab94-9723f5c30f1c@linaro.orgSigned-off-by:
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Arnd Bergmann authored
Merge tag 'imx-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/drivers i.MX drivers change for 6.3: - A couple of cleanups to drop device_driver owner setting from i.MX93 PD and SRC driver. - A series from Lucas Stach to add high performance PLL clock support for imx8mp-blk-ctrl driver. - A couple of changes to set LCDIF panic read hurry level for i.MX8M blk-ctrl drivers. - Use devm_platform_get_and_ioremap_resource() for imx-weim bus driver. * tag 'imx-drivers-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: soc: imx: imx8mp-blk-ctrl: set HDMI LCDIF panic read hurry level soc: imx: imx93-src: No need to set device_driver owner soc: imx: imx93-pd: No need to set device_driver owner soc: imx: imx8m-blk-ctrl: set LCDIF panic read hurry level soc: imx: imx8mp-blk-ctrl: expose high performance PLL clock soc: imx: imx8mp-blk-ctrl: add instance specific probe function soc: imx: add Kconfig symbols for blk-ctrl drivers bus: imx-weim: use devm_platform_get_and_ioremap_resource() Link: https://lore.kernel.org/r/20230130023947.11780-1-shawnguo@kernel.orgSigned-off-by:
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https://github.com/Broadcom/stblinuxArnd Bergmann authored
This pull request contains Broadcom ARM/ARM64 SoCs drivers updates for 6.3, please pull the following: - Uwe removes an empty platform driver remove function in the bcm2835-power driver * tag 'arm-soc/for-6.3/drivers' of https://github.com/Broadcom/stblinux: soc: bcm: bcm2835-power: Drop empty platform remove function Link: https://lore.kernel.org/r/20230128193844.1628888-1-f.fainelli@gmail.comSigned-off-by:
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Arnd Bergmann authored
Merge tag 'sunxi-drivers-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into soc/drivers - introduce Allwinner PPU driver - limit iteration in sram debugfs * tag 'sunxi-drivers-for-6.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: soc: sunxi: Add Allwinner D1 PPU driver dt-bindings: power: Add Allwinner D1 PPU soc: sunxi: sram: Only iterate over SRAM children Link: https://lore.kernel.org/r/Y9RXXATRNqEv0GJT@jernej-laptopSigned-off-by:
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Arnd Bergmann authored
Merge tag 'renesas-drivers-for-v6.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers Renesas driver updates for v6.3 (take two) - Add support for the Renesas RZ/V2M External Power Sequence Controller (PWC). * tag 'renesas-drivers-for-v6.3-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: soc: renesas: Add PWC support for RZ/V2M Link: https://lore.kernel.org/r/cover.1674815095.git.geert+renesas@glider.beSigned-off-by:
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Arnd Bergmann authored
Merge tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.3-mw0 It's all StarFive stuff this time: Their new JH7110 SoC uses a SiFive core complex, and therefore a SiFive cache controller too. That needed a compatible added to both the binding and driver. The JH7110 also has power domains, which are supported by a new driver and a corresponding dt-binding. Signed-off-by:
Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-for-v6.3-mw0' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: soc: starfive: Add StarFive JH71XX pmu driver dt-bindings: power: Add starfive,jh7110-pmu soc: sifive: ccache: Add StarFive JH7110 support dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC Link: https://lore.kernel.org/r/Y9LNIm9pkr+Owv/e@spudSigned-off-by:
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Roy-CW.Yeh authored
Add MT8195 VPPSYS0 and VPPSYS1 driver data. Signed-off-by:
Roy-CW.Yeh <roy-cw.yeh@mediatek.com> Signed-off-by:
Moudy Ho <moudy.ho@mediatek.com> Reviewed-by:
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Moudy Ho authored
For MT8195, VPPSYS0 and VPPSYS1 are 2 display pipes with hardware differences in power domains, clocks and subsystem counts, which should be determined by compatible names. Signed-off-by:
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20230118031509.29834-3-moudy.ho@mediatek.comSigned-off-by:
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AngeloGioacchino Del Regno authored
This driver currently deals with GPU-SRAM regulator coupling, ensuring that the SRAM voltage is always between a specific range of distance to the GPU voltage, depending on the SoC, necessary in order to achieve system stability across the full range of supported GPU frequencies. Signed-off-by:
Dmitry Osipenko <dmitry.osipenko@collabora.com> Reviewed-by:
Alyssa Rosenzweig <alyssa@collabora.com> Link: https://lore.kernel.org/r/20221006115816.66853-1-angelogioacchino.delregno@collabora.comSigned-off-by:
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Lucas Stach authored
Same as done for both LCDIF interfaces in the MEDIA domain, set the panic priority of the LCDIF instance in the HDMI domain to the maximium NoC priority of 7 to minimize chances of display underflows. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Reviewed-by:
Peng Fan <peng.fan@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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- 27 Jan, 2023 2 commits
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Samuel Holland authored
The PPU contains a series of identical MMIO register ranges, one for each power domain. Each range contains control/status bits for a clock gate, reset line, output gates, and a power switch. (The clock and reset are separate from, and in addition to, the bits in the CCU.) It also contains a hardware power sequence engine to control the other bits. Acked-by:
Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20230126063419.15971-3-samuel@sholland.orgSigned-off-by:
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Samuel Holland authored
The Allwinner D1 family of SoCs contain a PPU power domain controller separate from the PRCM. It can power down the video engine and DSP, and it contains special logic for hardware-assisted CPU idle. Other recent Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains. Reviewed-by:
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- 25 Jan, 2023 12 commits
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Ricardo Ribalda authored
If the system does not come from reset (like when is booted via kexec()), the peripheral might triger an IRQ before the data structures are initialised. Fixes: [ 0.227710] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000f08 [ 0.227913] Call trace: [ 0.227918] svs_isr+0x8c/0x538 Signed-off-by:
Ricardo Ribalda <ribalda@chromium.org> Link: https://lore.kernel.org/r/20221127-mtk-svs-v2-0-145b07663ea8@chromium.orgSigned-off-by:
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Nancy.Lin authored
Add mtk-mutex support for mt8195 vdosys1. The vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. Ovl_adaptor is composed of several sub-elements which include MDP_RDMA0~7, MERGE0~3, and ETHDR. Signed-off-by:
Nancy.Lin <nancy.lin@mediatek.com> Reviewed-by:
CK Hu <ck.hu@mediatek.com> Tested-by:
Bo-Chen Chen <rex-bc.chen@mediatek.com> Link: https://lore.kernel.org/r/20230113104434.28023-12-nancy.lin@mediatek.comSigned-off-by:
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Nancy.Lin authored
Add mtk-mutex DDP_COMPONENT_DP_INTF1 component. The MT8195 vdosys1 path component contains ovl_adaptor, merge5, and dp_intf1. It is a preparation for adding support for MT8195 vdosys1 path component. Signed-off-by:
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Nancy.Lin authored
MT8195 vdosys1 has more than 32 reset bits and a different reset base than other chips. Add the number of reset bits and reset base in mmsys private data. Signed-off-by:
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Nancy.Lin authored
Add mmsys for support 64 reset bits. It is a preparation for MT8195 vdosys1 HW reset. MT8195 vdosys1 has more than 32 reset bits. 1. Add the number of reset bits in mmsys private data 2. move the whole "reset register code section" behind the "get mmsys->data" code section for getting the num_resets in mmsys->data. Signed-off-by:
Nícolas F. R. A. Prado <nfraprado@collabora.com> Link: https://lore.kernel.org/r/20230113104434.28023-9-nancy.lin@mediatek.comSigned-off-by:
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Nancy.Lin authored
Add cmdq support for mtk-mmsys config API. The mmsys config register settings need to take effect with the other HW settings(like OVL_ADAPTOR...) at the same vblanking time. If we use CPU to write the mmsys reg, we can't guarantee all the settings can be written in the same vblanking time. Cmdq is used for this purpose. We prepare all the related HW settings in one cmdq packet. The first command in the packet is "wait stream done", and then following with all the HW settings. After the cmdq packet is flush to GCE HW. The GCE waits for the "stream done event" to coming and then starts flushing all the HW settings. This can guarantee all the settings flush in the same vblanking. Signed-off-by:
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Nancy.Lin authored
Add four mmsys config APIs. The config APIs are used for config mmsys reg. Some mmsys regs need to be set according to the HW engine binding to the mmsys simultaneously. 1. mtk_mmsys_merge_async_config: config merge async width/height. async is used for cross-clock domain synchronization. 2. mtk_mmsys_hdr_confing: config hdr backend async width/height. 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config: config mixer related settings. Signed-off-by:
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Nancy.Lin authored
Simplify code for update mmsys reg. Signed-off-by:
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Nancy.Lin authored
Add mt8195 vdosys1 routing table to the driver data of mtk-mmsys. Signed-off-by:
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Nancy.Lin authored
Add new mmsys component: ethdr_mixer and mdp_rdma. These components will use in mt8195 vdosys1. Signed-off-by:
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Nancy.Lin authored
Add vdosys1 reset control bit for MT8195 platform. Signed-off-by:
Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by:
Philipp Zabel <p.zabel@pengutronix.de> Tested-by:
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Nancy.Lin authored
Add vdosys1 mmsys compatible for MT8195 platform. For MT8195, VDOSYS0 and VDOSYS1 are 2 display HW pipelines binding to 2 different power domains, different clock drivers and different mediatek-drm drivers. Signed-off-by:
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- 24 Jan, 2023 1 commit
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Arnd Bergmann authored
Merge tag 'memory-controller-drv-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers Memory controller drivers for v6.3 1. TI Emif: simplify device_get_match_data(). 2. Renesas RPC IF: - Few fixes (decouple driver's private data structure from other drivers; unbind and rebind due to triggering managed resources allocation from other drivers); - Bigger rework around improved runtime Power Management. * tag 'memory-controller-drv-6.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: ti-emif-pm: Use device_get_match_data() to simplify the code memory: renesas-rpc-if: Remove Runtime PM wrappers memory: renesas-rpc-if: Pass device instead of rpcif to rpcif_*() memory: renesas-rpc-if: Improve Runtime PM handling memory: renesas-rpc-if: Always use dev in rpcif_probe() memory: renesas-rpc-if: Move resource acquisition to .probe() memory: renesas-rpc-if: Split-off private data from struct rpcif Link: https://lore.kernel.org/r/20230123105330.63709-1-krzysztof.kozlowski@linaro.orgSigned-off-by:
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