- 09 Oct, 2023 32 commits
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Muhammad Ansari authored
[WHY] FreeSync spec requires PB8 and PB12 to be set to nominal refresh rate regardless of fixed rate or variable [HOW] Removed the condition that checks and overwrites max refresh rate and set PB8/PB12 to be set to max refresh rate always Reviewed-by:
Anthony Koo <anthony.koo@amd.com> Acked-by:
Tom Chung <chiahsuan.chung@amd.com> Signed-off-by:
Muhammad Ansari <muhammad.ansari@amd.com> Tested-by:
Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Sung Joon Kim authored
[why] It's important to make sure SMU messages are logged by default to improve debugging for power optimization use cases. [how] Change logs to warnings when SMU message returns non-success id. Reviewed-by:
Charlene Liu <charlene.liu@amd.com> Acked-by:
Sung Joon Kim <sungkim@amd.com> Tested-by:
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Stanley.Yang authored
The amdgpu_ras_get_context may return NULL if device not support ras feature, so add check before using. Signed-off-by:
Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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Yifan Zhang authored
With S/G display becomes stable, enable S/G display for recent APUs by default rather than white list. v2: explicitly disable sg on pre-CZ chips (Alex) v3: add parens for every clause (Alex) Co-authored-by:
Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by:
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Lijo Lazar authored
Add documentation for the newly added manufacturer and fru_id attributes in sysfs. Signed-off-by:
Lijo Lazar <lijo.lazar@amd.com> Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Lijo Lazar authored
Add support to read Manufacturer Name and FRU File Id fields. Also add sysfs device attributes for external usage. Signed-off-by:
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Lijo Lazar authored
Keep FRU related information together in a separate structure. Signed-off-by:
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Yang Wang authored
v1: enable GFX v9.4.3 FRU device to query board information. v2: use MP1 version to identify different asic Signed-off-by:
Yang Wang <kevinyang.wang@amd.com> Reviewed-by:
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Boyuan Zhang authored
Update IB starting address alignment and size alignment with correct values for decode and encode IPs. Decode IB starting address alignment: 256 bytes Decode IB size alignment: 64 bytes Encode IB starting address alignment: 256 bytes Encode IB size alignment: 4 bytes Also bump amdgpu driver version for this update. Signed-off-by:
Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Acked-by:
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Gabe Teeger authored
[what] does_configuration_meet_sw_policies check was not done in the validate_only portion of dml2, so some unsupported modes were passing bw validation, only to fail the same check later in validate_and_build. now we add the check to validate_only. Also add line in dcn35_resource to ensure that value set for enable_windowed_mpo_odm gets passed to dml. [why] Immediate black screen during video playback at 4k144hz. The debugger showed that we were failing validation in dml on every updateplanes(). Reviewed-by:
Wenjing Liu <wenjing.liu@amd.com> Acked-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by:
Gabe Teeger <gabe.teeger@amd.com> Signed-off-by:
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Daniel Miess authored
Update DML2 with replay vblank logic found in DML1. Reviewed-by:
Daniel Miess <daniel.miess@amd.com> Signed-off-by:
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Saaem Rizvi authored
[Why] There are certain cases during a transition to ODM that might cause corruption on the display. This occurs when we choose certain pipes in a particular state. [How] We now will store the pipe indexes of the any pipes that might be problematic to switch to during an ODM transition, and only use them as a last resort. Reviewed-by:
Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Acked-by:
Saaem Rizvi <syedsaaem.rizvi@amd.com> Signed-off-by:
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Charlene Liu authored
dc->dml2_options.use_native_pstate_optimization flag will make driver use dcn32 legacy_svp_drr related tuning. Set this to false fixed the stutter underflow issue also based on HW suggest disable ODM by default and let DML choose it. Reviewed-by:
Zhan Liu <zhan.liu@amd.com> Acked-by:
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Sung Joon Kim authored
[why] Surface height/width for Chroma has another variable that it should be intialized to, chroma_size. Fixing this will help pass DML2.0 validation for YCbCr420 tests, DCHB006.109,129, DCHB014.011,012. [how] Assign SurfaceHeight/WidthC to chroma_size.height/width Reviewed-by:
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Taimur Hassan authored
Rework dml2_map_dc_pipes to keep the logic clean. Reviewed-by:
Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by:
Taimur Hassan <syed.hassan@amd.com> Signed-off-by:
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Taimur Hassan authored
[Why & How] DML2 did not carry over DML1 logic that splits pipe for stero timings. Pipe splitting is needed in this case to pass stereo tests. Reviewed-by:
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Sung Joon Kim authored
[why] Regression from DML1.0 where we use differen DET buffer sizes for each pipe. From the spec, we need to use DET buffer size of 384 kb for each pipe [how] Ensure to use 384 kb DET buffer sizes for each available pipe. Reviewed-by:
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Sung Joon Kim authored
[why] There are cases where more than 1 stream can be mapped to the same surface. DML2.0 does not seem to handle these cases. [how] Make sure to account for the stream id when deriving the plane id. By doing this, each plane id will be unique based on the stream id. Reviewed-by:
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Charlene Liu authored
Add z8 watermarks to struct for later ASIC use. Reviewed-by:
Alvin Lee <alvin.lee2@amd.com> Acked-by:
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Qingqing Zhuo authored
Enable DML2 for DCN35. Changes since V1: - Remove hard coded values Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Roman Li <roman.li@amd.com> Signed-off-by:
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Qingqing Zhuo authored
DC is transitioning from DML to DML2, and this commit introduces all the required changes for some of the already available ASICs and adds the required code infra to support new ASICs under DML2. DML2 is also a generated code that provides better mode verification and programming models for software/hardware, and it enables a better way to create validation tools. This version is more like a middle step to the complete transition to the DML2 version. Changes since V1: - Alex: Fix typos Changes since V2: - Update DC includes Changes since V3: - Fix 32 bit compilation issues on x86 Changes since V4: - Avoid compilation of DML2 on some not supported 32-bit architecture - Update commit message Co-developed-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Rodrigo Siqueira authored
For some reason, the dml code is not guarded under CONFIG_DRM_AMD_DC_FP in the Makefile. This commit moves the dml code under the DC_FP guard. Reviewed-by:
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Rodrigo Siqueira authored
bw_fixed does not need any FPU operation, and it is used on DCE and DCN. For this reason, this commit moves bw_fixed to the basic folder outside DML. Reviewed-by:
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Rodrigo Siqueira authored
The custom_float file does not have any FPU operation, so it should be inside DML. This commit moves the file to the basic folder. Reviewed-by:
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Rodrigo Siqueira authored
dce_calcs does not have FPU operations, and it is required for DCE and DCN. Remove this file from the DML folder and add it to the basic folder visible for DCE and DCN. Reviewed-by:
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Alex Deucher authored
When ROCm is active enable additional SMU 13.0.0 optimizations. This reuses the unused powersave profile on PMFW. v2: move to the swsmu code since we need both bits active in the workload mask. Reviewed-by: -
Sebastian Andrzej Siewior authored
dcn20_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. To preserve previous "clean" state of "pipes" add a memset() before the second invocation of dcn20_validate_bandwidth_internal() where the variable is used. Acked-by:
Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by:
Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by:
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Sebastian Andrzej Siewior authored
dcn21_validate_bandwidth_fp() is invoked while FPU access has been enabled. FPU access requires disabling preemption even on PREEMPT_RT. It is not possible to allocate memory with disabled preemption even with GFP_ATOMIC on PREEMPT_RT. Move the memory allocation before FPU access is enabled. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928Acked-by:
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Sebastian Andrzej Siewior authored
Add a warning if the FPU is used from any context other than task context. This is only precaution since the code is not able to be used from softirq while the API allows it on x86 for instance. Acked-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2036742Signed-off-by:
Mario Limonciello <mario.limonciello@amd.com> Acked-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by:
Felix Held <felix.held@amd.com> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2894Signed-off-by:
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Mario Limonciello authored
For pptable structs that use flexible array sizes, use flexible arrays. Suggested-by:
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- 05 Oct, 2023 8 commits
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Kees Cook authored
Prepare for the coming implementation by GCC and Clang of the __counted_by attribute. Flexible array members annotated with __counted_by can have their accesses bounds-checked at run-time via CONFIG_UBSAN_BOUNDS (for array indexing) and CONFIG_FORTIFY_SOURCE (for strcpy/memcpy-family functions). As found with Coccinelle[1], add __counted_by for struct amdgpu_bo_list. Additionally, since the element count member must be set before accessing the annotated flexible array member, move its initialization earlier. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Cc: David Airlie <airlied@gmail.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: "Gustavo A. R. Silva" <gustavoars@kernel.org> Cc: Luben Tuikov <luben.tuikov@amd.com> Cc: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Cc: Felix Kuehling <Felix.Kuehling@amd.com> Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Cc: linux-hardening@vger.kernel.org Link: https://github.com/kees/kernel-tools/blob/trunk/coccinelle/examples/counted_by.cocci [1] Reviewed-by:
Luben Tuikov <luben.tuikov@amd.com> Reviewed-by:
Kees Cook <keescook@chromium.org> Signed-off-by:
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Srinivasan Shanmugam authored
There is no reason to call return at the end of function that returns void. Fixes the below: WARNING: void function return statements are not generally useful Thus remove such a statement in the affected functions. Cc: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: "Pan, Xinhui" <Xinhui.Pan@amd.com> Signed-off-by:
Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by:
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Lijo Lazar authored
Add documentation for board info sysfs attribute. Signed-off-by:
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Lijo Lazar authored
Add a sysfs attribute which shows the board form factor like OAM or CEM. Signed-off-by:
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Lijo Lazar authored
Add support to query package types supported in smuio v13.0 ASICs. Signed-off-by:
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Lijo Lazar authored
Expand support to get other board types like OAM or CEM. Signed-off-by:
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Sathishkumar S authored
fix wrong ip count INFO on spatial partitions. update the query to return the instance count corresponding to the partition id. v2: initialize variables only when required to be (Christian) move variable declarations to the beginning of function (Christian) Signed-off-by:
Sathishkumar S <sathishkumar.sundararaju@amd.com> Acked-by:
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Asad Kamal authored
Remove set df cstate as disallow df state is not required for SMUv13.0.6 Signed-off-by:
Asad Kamal <asad.kamal@amd.com> Reviewed-by:
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