- 02 Oct, 2020 25 commits
-
-
Julia Lawall authored
Replace commas with semicolons. What is done is essentially described by the following Coccinelle semantic patch (http://coccinelle.lip6.fr/): // <smpl> @@ expression e1,e2; @@ e1 -, +; e2 ... when any // </smpl> Signed-off-by:
Julia Lawall <Julia.Lawall@inria.fr> Signed-off-by:
Herbert Xu <herbert@gondor.apana.org.au>
-
Ard Biesheuvel authored
Currently, we use the jiffies counter as a time source, by staring at it until a HZ period elapses, and then staring at it again and perform as many XOR operations as we can at the same time until another HZ period elapses, so that we can calculate the throughput. This takes longer than necessary, and depends on HZ, which is undesirable, since HZ is system dependent. Let's use the ktime interface instead, and use it to time a fixed number of XOR operations, which can be done much faster, and makes the time spent depend on the performance level of the system itself, which is much more reasonable. To ensure that we have the resolution we need even on systems with 32 kHz time sources, while not spending too much time in the benchmark on a slow CPU, let's switch to 3 attempts of 800 repetitions each: that way, we will only misidentify algorithms that perform within 10% of each other as the fastest if they are faster than 10 GB/s to begin with, which is not expected to occur on systems with such coarse clocks. On ThunderX2, I get the following results: Before: [72625.956765] xor: measuring software checksum speed [72625.993104] 8regs : 10169.000 MB/sec [72626.033099] 32regs : 12050.000 MB/sec [72626.073095] arm64_neon: 11100.000 MB/sec [72626.073097] xor: using function: 32regs (12050.000 MB/sec) After: [72599.650216] xor: measuring software checksum speed [72599.651188] 8regs : 10491 MB/sec [72599.652006] 32regs : 12345 MB/sec [72599.652871] arm64_neon : 11402 MB/sec [72599.652873] xor: using function: 32regs (12345 MB/sec) Link: https://lore.kernel.org/linux-crypto/20200923182230.22715-3-ardb@kernel.org/Signed-off-by:
Ard Biesheuvel <ardb@kernel.org> Reviewed-by:
Douglas Anderson <dianders@chromium.org> Signed-off-by:
-
Ard Biesheuvel authored
Currently, the XOR module performs its boot time benchmark at core initcall time when it is built-in, to ensure that the RAID code can make use of it when it is built-in as well. Let's defer this to a later stage during the boot, to avoid impacting the overall boot time of the system. Instead, just pick an arbitrary implementation from the list, and use that as the preliminary default. Reviewed-by:
-
Sihang Chen authored
The 'qm->curr_qm_qp_num' is not initialized, which will result in failure to write the current_q file. Signed-off-by:
Sihang Chen <chensihang1@hisilicon.com> Signed-off-by:
Yang Shen <shenyang39@huawei.com> Reviewed-by:
Zhou Wang <wangzhou1@hisilicon.com> Signed-off-by:
-
Yang Shen authored
As before, when the ZIP device is too busy to creat a request, it will return '-EBUSY'. But the crypto process think the '-EBUSY' means a successful request and wait for its completion. So replace '-EBUSY' with '-EAGAIN' to show crypto this request is failed. Fixes: 62c455ca("crypto: hisilicon - add HiSilicon ZIP...") Signed-off-by:
-
Zhou Wang authored
The zero length input will cause a call trace when use GZIP decompress like this: Unable to handle kernel paging request at virtual address ... lr : get_gzip_head_size+0x7c/0xd0 [hisi_zip] Judge the input length and return '-EINVAL' when input is invalid. Fixes: 62c455ca("crypto: hisilicon - add HiSilicon ZIP...") Signed-off-by: -
Hao Fang authored
ZIP debug registers aren't cleared even if its driver is removed, so add a clearing operation when remove driver. Signed-off-by:
Hao Fang <fanghao11@huawei.com> Signed-off-by:
-
Herbert Xu authored
This patch removes a number of unused variables and marks others as unused in order to silence compiler warnings about them. Fixes: a8ea8bdd ("lib/mpi: Extend the MPI library") Signed-off-by:
Tianjia Zhang <tianjia.zhang@linux.alibaba.com> Signed-off-by:
-
Herbert Xu authored
This patch removes a few ineffectual assignments from the function crypto_poly1305_setdctxkey. Reported-by:
kernel test robot <lkp@intel.com> Signed-off-by:
-
Tomer Maimon authored
Modify the read size to the correct HW random registers size, 8bit. The incorrect read size caused and faulty HW random value. Signed-off-by:
Tomer Maimon <tmaimon77@gmail.com> Signed-off-by:
-
Peter Ujfalusi authored
Make sure that we call the dma_unmap_sg on the correct scatterlist on completion with the correct sg_nents. Use sg_table to managed the DMA mapping and at the same time add the needed dma_sync calls for the sg_table. Signed-off-by:
Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by:
-
Andrei Botila authored
Newer CAAM versions (Era 9+) support 16B IVs. Since for these devices the HW limitation is no longer present newer version should process the requests containing 16B IVs directly in hardware without using a fallback. Signed-off-by:
Andrei Botila <andrei.botila@nxp.com> Reviewed-by:
Horia Geantă <horia.geanta@nxp.com> Signed-off-by:
-
Andrei Botila authored
Newer CAAM versions (Era 9+) support 16B IVs. Since for these devices the HW limitation is no longer present newer version should process the requests containing 16B IVs directly in hardware without using a fallback. Signed-off-by:
-
Andrei Botila authored
Newer CAAM versions (Era 9+) support 16B IVs. Since for these devices the HW limitation is no longer present newer version should process the requests containing 16B IVs directly in hardware without using a fallback. Signed-off-by:
-
Andrei Botila authored
XTS should not return succes when dealing with block length equal to zero. This is different than the rest of the skcipher algorithms. Fixes: 31bb2f0d ("crypto: caam - check zero-length input") Cc: <stable@vger.kernel.org> # v5.4+ Signed-off-by:
-
Andrei Botila authored
CAAM accelerator only supports XTS-AES-128 and XTS-AES-256 since it adheres strictly to the standard. All the other key lengths are accepted and processed through a fallback as long as they pass the xts_verify_key() checks. Fixes: 226853ac ("crypto: caam/qi2 - add skcipher algorithms") Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by:
-
Andrei Botila authored
CAAM accelerator only supports XTS-AES-128 and XTS-AES-256 since it adheres strictly to the standard. All the other key lengths are accepted and processed through a fallback as long as they pass the xts_verify_key() checks. Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Cc: <stable@vger.kernel.org> # v4.12+ Signed-off-by:
-
Andrei Botila authored
CAAM accelerator only supports XTS-AES-128 and XTS-AES-256 since it adheres strictly to the standard. All the other key lengths are accepted and processed through a fallback as long as they pass the xts_verify_key() checks. Fixes: c6415a60 ("crypto: caam - add support for acipher xts(aes)") Cc: <stable@vger.kernel.org> # v4.4+ Signed-off-by:
-
Andrei Botila authored
A hardware limitation exists for CAAM until Era 9 which restricts the accelerator to IVs with only 8 bytes. When CAAM has a lower era a fallback is necessary to process 16 bytes IV. Fixes: 226853ac ("crypto: caam/qi2 - add skcipher algorithms") Cc: <stable@vger.kernel.org> # v4.20+ Signed-off-by:
-
Andrei Botila authored
A hardware limitation exists for CAAM until Era 9 which restricts the accelerator to IVs with only 8 bytes. When CAAM has a lower era a fallback is necessary to process 16 bytes IV. Fixes: b189817c ("crypto: caam/qi - add ablkcipher and authenc algorithms") Cc: <stable@vger.kernel.org> # v4.12+ Signed-off-by:
-
Andrei Botila authored
A hardware limitation exists for CAAM until Era 9 which restricts the accelerator to IVs with only 8 bytes. When CAAM has a lower era a fallback is necessary to process 16 bytes IV. Fixes: c6415a60 ("crypto: caam - add support for acipher xts(aes)") Cc: <stable@vger.kernel.org> # v4.4+ Signed-off-by:
-
Qinglang Miao authored
Simplify the return expression. Signed-off-by:
Qinglang Miao <miaoqinglang@huawei.com> Signed-off-by:
-
Qinglang Miao authored
Simplify the return expression. Signed-off-by:
-
Pavel Machek authored
Fix resource leak in error handling. Signed-off-by:
Pavel Machek (CIP) <pavel@denx.de> Acked-by:
John Allen <john.allen@amd.com> Signed-off-by:
-
Liu Shixin authored
Simplify the return expression. Signed-off-by:
Liu Shixin <liushixin2@huawei.com> Signed-off-by:
-
- 25 Sep, 2020 15 commits
-
-
Tianjia Zhang authored
Asymmetric digsig supports SM2-with-SM3 algorithm combination, so that IMA can also verify SM2's signature data. Signed-off-by:
Xufeng Zhang <yunbo.xufeng@linux.alibaba.com> Reviewed-by:
Mimi Zohar <zohar@linux.ibm.com> Reviewed-by:
Vitaly Chikunov <vt@altlinux.org> Signed-off-by:
-
Tianjia Zhang authored
The digital certificate format based on SM2 crypto algorithm as specified in GM/T 0015-2012. It was published by State Encryption Management Bureau, China. The method of generating Other User Information is defined as ZA=H256(ENTLA || IDA || a || b || xG || yG || xA || yA), it also specified in https://tools.ietf.org/html/draft-shen-sm2-ecdsa-02. The x509 certificate supports SM2-with-SM3 type certificate verification. Because certificate verification requires ZA in addition to tbs data, ZA also depends on elliptic curve parameters and public key data, so you need to access tbs in sig and calculate ZA. Finally calculate the digest of the signature and complete the verification work. The calculation process of ZA is declared in specifications GM/T 0009-2012 and GM/T 0003.2-2012. Signed-off-by:
Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by:
-
Tianjia Zhang authored
The digital certificate format based on SM2 crypto algorithm as specified in GM/T 0015-2012. It was published by State Encryption Management Bureau, China. This patch adds the OID object identifier defined by OSCCA. The x509 certificate supports SM2-with-SM3 type certificate parsing. It uses the standard elliptic curve public key, and the sm2 algorithm signs the hash generated by sm3. Signed-off-by:
-
Tianjia Zhang authored
Add testmgr test vectors for SM2 algorithm. These vectors come from `openssl pkeyutl -sign` and libgcrypt. Signed-off-by:
-
Tianjia Zhang authored
When the 'key' allocation fails, the 'req' will not be released, which will cause memory leakage on this path. This patch adds a 'free_req' tag used to solve this problem, and two new err values are added to reflect the real reason of the error. Signed-off-by:
-
Tianjia Zhang authored
Some asymmetric algorithms will get different ciphertext after each encryption, such as SM2, and let testmgr support the testing of such algorithms. In struct akcipher_testvec, set c and c_size to be empty, skip the comparison of the ciphertext, and compare the decrypted plaintext with m to achieve the test purpose. Signed-off-by:
-
Tianjia Zhang authored
This new module implement the SM2 public key algorithm. It was published by State Encryption Management Bureau, China. List of specifications for SM2 elliptic curve public key cryptography: * GM/T 0003.1-2012 * GM/T 0003.2-2012 * GM/T 0003.3-2012 * GM/T 0003.4-2012 * GM/T 0003.5-2012 IETF: https://tools.ietf.org/html/draft-shen-sm2-ecdsa-02 oscca: http://www.oscca.gov.cn/sca/xxgk/2010-12/17/content_1002386.shtml scctc: http://www.gmbz.org.cn/main/bzlb.htmlSigned-off-by:
-
Tianjia Zhang authored
The implementation of EC is introduced from libgcrypt as the basic algorithm of elliptic curve, which can be more perfectly integrated with MPI implementation. Some other algorithms will be developed based on mpi ecc, such as SM2. Signed-off-by:
-
Tianjia Zhang authored
Expand the mpi library based on libgcrypt, and the ECC algorithm of mpi based on libgcrypt requires these functions. Some other algorithms will be developed based on mpi ecc, such as SM2. Signed-off-by:
-
Tianjia Zhang authored
Both crypto_sm3_update and crypto_sm3_finup have been exported, exporting crypto_sm3_final, to avoid having to use crypto_sm3_finup(desc, NULL, 0, dgst) to calculate the hash in some cases. Signed-off-by:
-
Weili Qian authored
'qm_init_qp_status' is just a help function to initiate some 'QP' status. 'QP' status should be updated separately. This patch removes the updating flags in 'QP' status. Signed-off-by:
Weili Qian <qianweili@huawei.com> Reviewed-by:
-
Yang Shen authored
The parameter type of 'pci_set_drvdata' is 'struct hisi_qm', so here the return type of 'pci_get_drvdata' should be 'struct hisi_qm' too. Signed-off-by:
-
Meng Yu authored
Using 'g' not equal to 2 in dh algorithm may cause an error like this: arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: dh: Party A: generate public key test failed. err -22 11375.065672] dh alg: dh: test failed on vector 1, err=-22 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000080 hpre-dh self test failed arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000083 arm-smmu-v3 arm-smmu-v3.1.auto: 0x00000000000000c0 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000081 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000040 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received: arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000790000000010 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000120800000082 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000080 arm-smmu-v3 arm-smmu-v3.1.auto: 0x0000000000000000 hisi_hpre 0000:79:00.0: dat_rd_poison_int_set [error status=0x8] found hisi_hpre 0000:79:00.0: ooo_rdrsp_err_int_set [error status=0xfc00] found hisi_hpre 0000:79:00.0: Controller resetting... hisi_hpre 0000:79:00.0: Controller reset complete {2}[Hardware Error]: Hardware error from APEI Generic Hardware Error Source: 0 {2}[Hardware Error]: event severity: recoverable {2}[Hardware Error]: Error 0, type: recoverable {2}[Hardware Error]: section type: unknown, c8b328a8-9917-4af6-9a13-2e08ab2e7586 {2}[Hardware Error]: section length: 0x4c as we missed initiating 'msg->in'. Fixes: c8b4b477("crypto: hisilicon - add HiSilicon HPRE accelerator") Signed-off-by:Meng Yu <yumeng18@huawei.com> Reviewed-by:
Zaibo Xu <xuzaibo@huawei.com> Signed-off-by:
-
Meng Yu authored
Adjust some coding style to make code aligned. Signed-off-by:
-
Meng Yu authored
1. Remove unused member 'debug_root' in 'struct hpre_debug'; 2. The u64 cast is redundant in 'cpu_to_le64'. Fixes: 84897415("crypto: hisilicon - Add debugfs for HPRE") Fixes: dadbe4c1("crypto: hisilicon/hpre - update debugfs ...") Signed-off-by:
-
