- 05 Jul, 2018 40 commits
-
-
Darren Powell authored
Signed-off-by:
Darren Powell <darren.powell@amd.com> Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Sonny Jiang authored
Signed-off-by:
Sonny Jiang <sonny.jiang@amd.com> Acked-by:
Junwei Zhang <Jerry.Zhang@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
-
Mikita Lipski authored
[why] HDMI 2.0 fails to validate 4K@60 timing with 10 bpc [how] Adding a helper function that would verify if the display depth assigned would pass a bandwidth validation. Drop the display depth by one level till calculated pixel clk is lower than maximum TMDS clk. Bugzilla: https://bugs.freedesktop.org/106959Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Tested-by:
Mike Lothian <mike@fireburn.co.uk> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
-
Mikita Lipski authored
[why] HDMI EDID's VSDB contains spectial timings for specifically YCbCr 4:2:0 colour space. In those cases we need to verify if the mode provided is one of the special ones has to use YCbCr 4:2:0 pixel encoding for display info. [how] Verify if the mode is using specific ycbcr420 colour space with the help of DRM helper function and assign the mode to use ycbcr420 pixel encoding. Signed-off-by:
-
Darren Powell authored
Eliminating the warnings produced by sphinx when processing the sphinx comments in amdgpu_device.c & amdgpu_mn.c Signed-off-by:
-
Gustavo A. R. Silva authored
Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and feedback_divider to uint64_t in order to avoid multiple potential integer overflows and give the compiler complete information about the proper arithmetic to use. Notice that such constant and variables are used in contexts that expect expressions of type uint64_t (64 bits, unsigned). The current casts to uint64_t effectively apply to each expression as a whole, but they do not prevent them from being evaluated using 32-bit arithmetic instead of 64-bit arithmetic. Also, once the expressions are properly evaluated using 64-bit arithmentic, there is no need for the parentheses that enclose them. Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow") Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow") Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by:
-
Kees Cook authored
As already done treewide, switch from open-coded multiplication to 2-factor allocation helper. Signed-off-by:
Kees Cook <keescook@chromium.org> Reviewed-by:
-
Harry Wentland authored
That change was a merge gone bad. This reverts commit cb1d7eac. Signed-off-by:
-
Dan Carpenter authored
The ->info[] array has DAL_IRQ_SOURCES_NUMBER elements so this condition should be >= instead of > or we could read one element beyond the end of the array. Fixes: 4562236b ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
-
Rex Zhu authored
delete the same struct define in powerplay, share the struct with display. Acked-by:
Rex Zhu <Rex.Zhu@amd.com> Signed-off-by:
-
Rex Zhu authored
Set memory clocks same as soc clocks Acked-by:
-
Rex Zhu authored
powerplay/dpm export all interfaces in struct amd_pm_funcs. so call common exported interfaces instead of powerplay inner interfaces Also not include header file hwmgr.h Acked-by:
-
Rex Zhu authored
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by:
-
Alex Deucher authored
These functions duplicated functionality which was ultimately added to the pci core. All users of these functions have been ported to using the newly exposed pci functionality. These functions are no longer used, so drop them. Acked-by:
Dave Airlie <airlied@redhat.com> Signed-off-by:
-
Alex Deucher authored
This is the last user of drm_pcie_get_speed_cap_mask. Use the pci version so we can drop drm_pcie_get_speed_cap_mask. Acked-by:
-
Alex Deucher authored
Use the newly exported pci functions to get the link width and speed rather than using the drm duplicated versions. Also query the GPU link caps directly rather than hardcoding them. Acked-by:
-
Alex Deucher authored
Internal header used by the driver to specify pcie gen speeds of the asic and chipset. Acked-by:
-
Alex Deucher authored
So drivers can use them. This can be used to replace duplicate code in the drm subsystem. Acked-by:
Bjorn Helgaas <bhelgaas@google.com> Signed-off-by:
-
Alex Deucher authored
Use separate firmware path for amdgpu to avoid conflicts with radeon on SI parts. Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
-
Alex Deucher authored
Use separate firmware path for amdgpu to avoid conflicts with radeon on CIK parts. v2: squash in logic simplification (Alex) Reviewed-by:
-
Nicolai Hähnle authored
The buffer object backing the user fence is reserved using the non-user fence, i.e., as soon as the non-user fence is signaled, the user fence buffer object can be moved or even destroyed. Therefore, emit the user fence first. Both fences have the same cache invalidation behavior, so this should have no user-visible effect. Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
-
Rex Zhu authored
use smu_helper function smu_set_watermarks_for_clocks_ranges in vega12_set_watermarks_for_clocks_ranges. Reviewed-by:
-
Rex Zhu authored
use void * as function parameter type in order for extension. Acked-by:
-
rex zhu authored
powerplay can recalculate the number of active display Acked-by:
-
rex zhu authored
powerplay can notify smu to recalculates the maximum deep-sleep divider display allowed. Acked-by:
-
rex zhu authored
Select the lowest MCLK frequency that is within the tolerable latency defined in DISPALY Acked-by:
-
Rex Zhu authored
For HBM, 25us latency is enough for memory clock switch. Acked-by:
-
Rex Zhu authored
Convert clock unit 10KHz to KHz as the data sturct defined. e.g. struct pp_clock_with_latency { uint32_t clocks_in_khz; uint32_t latency_in_us; }; Meanwhile revert the same conversion in display side. Acked-by: -
Alex Deucher authored
Was missed when updating the uvd 6 module. Fixes: 1aac3c91 (drm/amdgpu: fix insert nop for UVD6 ring) Reviewed-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
-
Huang Rui authored
We still use legacy type of gem_object_create, it should update to ttm_bo_type now. Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
-
Dirk Hohndel (VMware) authored
This is dual licensed under GPL-2.0 or MIT. Acked-by:
Thomas Gleixner <tglx@linutronix.de> Signed-off-by:
Dirk Hohndel (VMware) <dirk@hohndel.org> Signed-off-by:
-
Dirk Hohndel (VMware) authored
This is dual licensed under GPL-2.0 or MIT. Acked-by:
-
Thomas Zimmermann authored
This patch unifies the naming of DRM functions for reference counting of struct drm_device. The resulting code is more aligned with the rest of the Linux kernel interfaces. Signed-off-by:
Thomas Zimmermann <contact@tzimmermann.org> Signed-off-by:
-
Alex Deucher authored
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by:
James Zhu <James.Zhu@amd.com> Reviewed-by:
-
Alex Deucher authored
Set the me instance in early init and use that rather than calculating the instance based on the ring pointer. Reviewed-by:
-
Alex Deucher authored
Should be using PCIELaneLow for the low clock level. Reviewed-by:
-
Alex Deucher authored
Should be mclk rather than sclk. Reviewed-by:
-
Alex Deucher authored
Need to swap before doing arthimetic on the values. Reviewed-by:
-
Alex Deucher authored
Values need to be swapped on big endian. Reviewed-by:
-
Alex Deucher authored
new_active_crtcs is a bitmask, new_active_crtc_count is the actual count. Reviewed-by:
-
